CN103871961B - 互连结构及其制造方法 - Google Patents

互连结构及其制造方法 Download PDF

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CN103871961B
CN103871961B CN201210550003.3A CN201210550003A CN103871961B CN 103871961 B CN103871961 B CN 103871961B CN 201210550003 A CN201210550003 A CN 201210550003A CN 103871961 B CN103871961 B CN 103871961B
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interconnection structure
manufacture method
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CN103871961A (zh
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周鸣
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

本发明提供一种互连结构及其制造方法。所述互连结构的制造方法包括：在基底上形成多孔介质层；对所述多孔介质层进行表面处理，以形成隔离层；在所述隔离层上形成硬掩模。本发明还提供一种如所述的互连结构的制造方法所形成的互连结构。本发明能减少互连结构及其制造方法中的鼓包缺陷。

Description

互连结构及其制造方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种互连结构及其制造方法。
背景技术
现今集成电路设计和制造领域所遇到的一个挑战是如何降低信号传输RC延迟(Resistive Capacitive delay)，对此，现在技术已经采用的一种方法是将铝金属层替换为铜金属层，降低金属层串联电阻；还有一种方法是降低金属层之间的寄生电容，这可以通过在金属层之间的介质层中构造多孔的(Porous)低介电常数(Low k)材料或者空气隙(AirGap)来实现。
在公开号为US7279427B2的美国专利中公开了一种互连结构的制造方法，参考图1，示出了所述美国专利中互连结构的示意图。所述互连结构的制造方法包括：提供基底5，所述基底5中形成有半导体元件；在基底5上形成低k介质层4；在低k介质层4上形成掩模6；通过所述掩模6对所述低k介质层4进行图形化，以形成通孔(图未示)；在所述通孔中填充金属材料，以形成于所述半导体元件相连的互连结构。具体地，所述低k介质层4为多孔低k介质层，所述掩模6为硬掩模。
然而实际工艺中发现，所述互连结构容易出现鼓包(bump defect)的缺陷。所述鼓包的缺陷容易造成互连结构的制造良率的下降，还会影响互连结构电连接的效果。
发明内容
本发明解决的是改善互连结构及其制造方法中容易出现鼓包缺陷的技术问题。
为解决上述问题，本发明提出了一种互连结构的制造方法，包括：在基底上形成多孔介质层；对所述多孔介质层进行表面处理，以形成隔离层；在所述隔离层上形成硬掩模。在多孔介质层上形成的隔离层，可以起到防止多孔介质层吸潮的作用，从而避免水分在所述多孔介质层上的吸附，进而避免水分吸附所引起的鼓包缺陷的问题。
可选地，在所述隔离层上形成硬掩模的步骤包括：在所述隔离层上形成多孔介质层硬掩模，在形成多孔介质层硬掩模之后还包括进行表面处理。可以进一步减少多孔介质层的吸潮问题，进而避免鼓包缺陷的产生。
可选地，在通过臭氧和二乙氧基甲基硅烷进行处理之前，还骤包括：通过臭氧进行预处理。通过臭氧对所述多孔介质层进行预处理，可以提高隔离层在多孔介质层上的粘附性，提高隔离层在多孔介质层上的附着效果，一方面可以提高薄膜质量、提高薄膜机械强度，另一方面还可以防止水汽的渗透，从而提高了隔离层的隔离效果。
可选地，形成多孔介质层的步骤包括：在基底上形成介质材料；对所述介质材料进行紫外光处理，以形成多孔介质层；所述表面处理的步骤包括：在所述紫外光处理的腔室中对所述多孔介质层进行原位的表面处理。通过原位方式进行表面处理，所述表面处理的步骤可以与现有设备实现良好的集成，此外，在进行表面处理时无需将待形成的互连结构从真空腔移至其他腔体内，可以减少工艺步骤，简化工艺。
附图说明
图1为现有技术中互连结构的制造方法的示意图；
图2至图7是本发明互连结构制造方法一实施例的示意图。
具体实施方式
在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施的限制。
其次，本发明利用示意图进行详细描述，在详述本发明实施例时，为便于说明，所述示意图只是实例，其在此不应限制本发明保护的范围。
为了解决现有技术的问题，发明人对现有技术中的互连结构进行了大量研究发现，互连结构中设置有多孔介质层时，所述多孔介质层由于多孔结构的存在，容易出现吸附环境中的水分(即发生吸潮现象)，吸附的水分残留在多孔介质层的表面，再在所述多孔介质层表面沉积其他膜层时，水分吸附的位置处容易产生鼓包(bump defects)的缺陷。
相应地，发明人提供了一种互连结构的制造方法，在形成多孔介质层之后，在多孔介质层上形成一层用于防止多孔介质层吸潮的隔离层，以避免鼓包缺陷的发生。
相应地，本发明提供一种互连结构的制造方法，大致包括以下步骤：
步骤S1，在基底上形成多孔介质层；
步骤S2，对所述多孔介质层进行表面处理，以形成隔离层；
步骤S3，在所述隔离层上形成硬掩模。
下面结合具体实施例对本发明技术方案做详细说明。
参考图2至7，示出了本发明互连结构制造方法第一实施例的示意图。所述互连结构的制造方法大致包括以下步骤：
如图2，执行步骤S1，提供基底100；本实施例中，所述基底100包括：形成有晶体管等半导体元件的衬底层(图未示)，形成于衬底层上的金属层(图未示)，形成于金属层上的阻挡层(图未示)。其中所述金属层用于通过本实施例形成的互连结构实现与其他器件的电连接。此处所述阻挡层用于防止金属层中金属的扩散。
具体地，金属层的材料为铜或铝。所述阻挡层的材料为掺氮的碳化硅(NitrogenDoped Silicon Carbon，NDC)。但是本发明对金属层和阻挡层的材料不作限制。
如图2，继续执行步骤S1，在基底100上形成介质材料101。
本实施例中，通过二乙氧基甲基硅烷和原子转移自由基聚合形成所述介质材料101。具体地，可以通过溶胶凝胶的方式形成所述介质材料101。但是本发明对介质材料101不作限制，对介质材料101的形成方式也不作限制。此处所述介质材料101还可以是SiO2、SiOF、SiCOH、SiO、SiCO、SiCON、黑金刚石中的一种或多种。可以通过化学气相沉积的方式沉积所述介质材料101。
如图3所示，继续执行步骤S1，对所述介质材料101进行紫外光处理，以形成多孔介质层102。具体地，通过紫外光的辅助热处理可以在介质材料中形成多孔结构，以形成多孔介质层102。
需要说明的是，本实施例通过紫外光处理的方式形成多孔介质层102。但是本发明对多孔介质层102的形成方式不作限制，在其他实施例中，还可以通过其他方式形成所述多孔介质层102。
结合参考图4和图5，执行步骤S2，对所述多孔介质层102进行表面处理，以形成隔离层103。
此处所形成的隔离层103用于减弱多孔介质层102的吸潮问题。需要说明的是，在本实施例中，所述隔离层103为含C、H、O、Si的致密薄膜，但是本发明对此不作限制，只要形成的所述隔离层103比多孔介质层102致密，就可以起到减化多孔介质层102吸潮的问题，进而起到防止在互连结构中形成鼓包缺陷的作用。
具体地，在本实施例中，所述表面处理的步骤包括：通过臭氧和二乙氧基甲基硅烷(dimethyldiethoxysilane，DEMS)(所述二乙氧基甲基硅烷包括八甲基环四硅氧烷(octamethylcyclotetrasiloxane，OMCTS)、正硅酸乙酯(TEOS)和硅烷)进行处理，以形成材料为C5H14O2Si的隔离层103。C5H14O2Si材料的隔离层103致密性良好，可以起到优良的防吸潮作用。
需要说明的是，本发明对表面处理使用的材料以及所形成的隔离层103的材料不做限制，还可以采用其他方式形成另一材料的隔离层103。例如：所述隔离层103还可以是二氧化硅。
需要说明的是，提供的臭氧和二乙氧基甲基硅烷的气体的总量过大容易造成材料的浪费，而提供的气体总量过小则较难形成隔离效果好的隔离层103。因此优选地，通过臭氧和二乙氧基甲基硅烷进行处理的过程中，腔室内气压位于4～7托，功率位于50～500瓦；臭氧和二乙氧基甲基硅烷的气体流量为100～1000标况毫升每分。此处采用的载气为氦气，所述氦气的流量为100～2000标况毫升每分。但是本发明对载气的种类不做限制，载气还可以是氩气。
由于本实施例通过紫外光处理的方式对介质材料102进行表面处理，以形成多孔介质层102。本实施例中，在通过臭氧和DEMS进行表面处理的过程中，在紫外光处理的腔室中对所述多孔介质层102进行原位的表面处理。
需要说明的是，通过原位方式进行表面处理，所述表面处理的步骤可以与现有设备实现良好的集成，此外，在进行表面处理时无需将待形成的互连结构从真空腔中去除并移至其他腔体内，可以减少工艺步骤，简化工艺。但是本发明对此不作限制，在其他实施例中，还可以不在紫外光处理的腔室中进行原位的表面处理，而是采用单独的步骤在单独的反应腔室中进行所述表面处理。
需要说明的是，优选地，在通过臭氧和二乙氧基甲基硅烷进行处理之前，还包括：通过臭氧进行预处理。
通过臭氧对所述多孔介质层102进行预处理，可以提高隔离层103在多孔介质层102上的粘附性，提高隔离层103在多孔介质层102上的附着效果，从而使隔离层103与多孔介质层102的结合更加紧密。一方面可以提高薄膜质量、提高薄膜机械强度，另一方面还可以防止水汽的渗透，从而提高了隔离层103的隔离效果。
需要说明的是，提供的臭氧的总量过大容易造成材料的浪费，而提供的臭氧的总量过小则不能起到提高隔离层103、多孔介质层102之间粘附性的作用。因此优选地，通过臭氧进行预处理的过程中，腔室内气压位于4～7托，功率位于50～500瓦；气体流量为100～1000标况毫升每分。
通过臭氧进行预处理的过程中也可以在紫外光处理的腔室中对所述多孔介质层102进行原位的表面处理。
结合参考图6和图7所示，执行步骤S3，在所述隔离层103上形成硬掩模。
具体地，本实施例中，形成硬掩模的步骤包括：依次在隔离层103上形成多孔介质层硬掩模104、TEOS硬掩模105、金属硬掩模106和氧化硅层107。但是本发明对此不作限制，在其他实施例中可以根据具体结构形成不同层的硬掩模。
需要说明的是，如图6所示，在隔离层103上形成多孔介质层硬掩模104之后，还可以对多孔介质层硬掩模104进行表面处理，以形成另一隔离层(图未示)，从而进一步减少多孔介质层102的吸潮问题，进而避免鼓包缺陷的产生。
此处进行表面处理的步骤包括：通过臭氧和二乙氧基甲基硅烷(dimethyldiethoxysilane，DEMS)(所述二乙氧基甲基硅烷包括八甲基环四硅氧烷(octamethylcyclotetrasiloxane，OMCTS)、正硅酸乙酯(TEOS)和硅烷)进行处理，以形成材料为C5H14O2Si的隔离层。
进行所述表面处理的具体工艺条件为：通过臭氧和二乙氧基甲基硅烷进行处理的过程中，腔室内气压位于4～7托，功率位于50～500瓦；臭氧和二乙氧基甲基硅烷的气体流量为100～1000标况毫升每分；载气为氦气，所述氦气的流量为100～2000标况毫升每分。
还可以在通过臭氧和二乙氧基甲基硅烷进行处理之前，还包括：通过臭氧进行预处理。通过臭氧对所述多孔介质层硬掩模104进行预处理，可以提高隔离层在多孔介质层硬掩模104上的粘附性，提高隔离层在多孔介质层硬掩模104上的附着效果，从而使隔离层与多孔介质层硬掩模104更加紧密。在提高薄膜质量的同时提高隔离层的隔离效果。
具体地，通过臭氧进行预处理的过程中，腔室内气压位于4～7托，功率位于50～500瓦；气体流量为100～1000标况毫升每分。
需要说明的是，在形成硬掩模之后，还包括：通过硬掩模图形化所述多孔介质层102以形成通孔，继续图形化多孔介质层102下的阻挡层以露出金属层，向所述通孔中填充金属材料以形成插塞等的步骤。所述步骤与现有技术相同，在此不再赘述。
本发明提供的互连结构的制造方法，抑制了鼓包缺陷的发生，提高了互连结构的制造良率。
相应地，本发明还提供了一种由所述的互连结构的制造方法所形成的互连结构。所述互连结构的制造方法可参考上述内容，此处不再赘述。
通过所述制造方法形成的互连结构具有较少或者没有鼓包缺陷，提高了互连结构电性连接可靠性。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (9)

1.一种互连结构的制造方法，其特征在于，包括：
在基底上形成介质材料；
对所述介质材料进行紫外光处理，形成多孔介质层；
对所述多孔介质层进行表面处理，以形成粘附在所述多孔介质层表面的隔离层；
依次在所述隔离层上形成多孔介质层硬掩膜、TEOS硬掩膜、金属硬掩膜和氧化硅层；在形成多孔介质层硬掩膜之后，对多孔介质层硬掩膜进行表面处理，以形成另一隔离层。
2.如权利要求1所述的互连结构的制造方法，其特征在于，所述表面处理的步骤包括：通过臭氧和二乙氧基甲基硅烷进行处理。
3.如权利要求2所述的互连结构的制造方法，其特征在于，在通过臭氧和二乙氧基甲基硅烷进行处理之前，还包括：通过臭氧进行预处理。
4.如权利要求2所述的互连结构的制造方法，其特征在于，通过臭氧和二乙氧基甲基硅烷进行处理的过程中，腔室内气压位于4～7托，功率位于50～500瓦；臭氧和二乙氧基甲基硅烷的气体流量为100～1000标况毫升每分；载气为氦气，所述氦气的流量为100～2000标况毫升每分。
5.如权利要求3所述的互连结构的制造方法，其特征在于，通过臭氧进行预处理的过程中，腔室内气压位于4～7托，功率位于50～500瓦；气体流量为100～1000标况毫升每分。
6.如权利要求1所述的互连结构的制造方法，其特征在于，所述多孔介质层的材料为SiO2、SiOF、SiCOH、SiO、SiCO、SiCON中的一种或多种。
7.如权利要求1所述的互连结构的制造方法，其特征在于，所述隔离层的材料为C5H14O2Si。
8.如权利要求1所述的互连结构的制造方法，其特征在于，所述表面处理的步骤包括：在所述紫外光处理的腔室中对所述多孔介质层进行原位的表面处理。
9.一种如权利要求1-8中任意一权利要求所述的互连结构的制造方法所形成的互连结构。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105244257B (zh) * 2014-07-08 2020-06-23 中芯国际集成电路制造(上海)有限公司 改善多孔低k薄膜的突起缺陷的方法
CN105633006B (zh) * 2014-10-30 2019-01-22 中芯国际集成电路制造(上海)有限公司 互连结构及其制作方法
CN110114870B (zh) * 2016-12-28 2023-07-21 株式会社村田制作所 电路模块
US10115679B1 (en) 2017-06-19 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Trench structure and method
CN112563143B (zh) * 2019-09-25 2022-03-22 长鑫存储技术有限公司 半导体结构制造方法
US11424187B2 (en) * 2020-08-04 2022-08-23 Nanya Technology Corporation Semiconductor device with porous insulating layers and method for fabricating the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102157441A (zh) * 2007-04-25 2011-08-17 联华电子股份有限公司 复合覆盖层的制作方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766287A (ja) * 1993-08-23 1995-03-10 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20020076935A1 (en) * 1997-10-22 2002-06-20 Karen Maex Anisotropic etching of organic-containing insulating layers
US6054379A (en) * 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6221745B1 (en) * 1998-11-27 2001-04-24 Taiwan Semiconductor Manufacturing Company High selectivity mask oxide etching to suppress silicon pits
US20070042580A1 (en) * 2000-08-10 2007-02-22 Amir Al-Bayati Ion implanted insulator material with reduced dielectric constant
US6933586B2 (en) * 2001-12-13 2005-08-23 International Business Machines Corporation Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens
US7238604B2 (en) * 2003-04-24 2007-07-03 Intel Corporation Forming thin hard mask over air gap or porous dielectric
US7547643B2 (en) * 2004-03-31 2009-06-16 Applied Materials, Inc. Techniques promoting adhesion of porous low K film to underlying barrier layer
WO2007036922A1 (en) * 2005-09-30 2007-04-05 Timothy Cummins An integrated electronic sensor
US7279427B2 (en) 2005-08-03 2007-10-09 Tokyo Electron, Ltd. Damage-free ashing process and system for post low-k etch
US7838428B2 (en) * 2006-03-23 2010-11-23 International Business Machines Corporation Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species
JP2008042077A (ja) * 2006-08-09 2008-02-21 Renesas Technology Corp 半導体装置及びその製造方法
US7851232B2 (en) * 2006-10-30 2010-12-14 Novellus Systems, Inc. UV treatment for carbon-containing low-k dielectric repair in semiconductor processing
US7655556B2 (en) * 2007-03-23 2010-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for semiconductor devices
US8173537B1 (en) * 2007-03-29 2012-05-08 Novellus Systems, Inc. Methods for reducing UV and dielectric diffusion barrier interaction
US7858532B2 (en) * 2007-08-06 2010-12-28 United Microelectronics Corp. Dielectric layer structure and manufacturing method thereof
US7879683B2 (en) * 2007-10-09 2011-02-01 Applied Materials, Inc. Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay
US8637396B2 (en) * 2008-12-01 2014-01-28 Air Products And Chemicals, Inc. Dielectric barrier deposition using oxygen containing precursor
US8435891B2 (en) * 2011-06-02 2013-05-07 International Business Machines Corporation Converting metal mask to metal-oxide etch stop layer and related semiconductor structure
US8648465B2 (en) * 2011-09-28 2014-02-11 International Business Machines Corporation Semiconductor interconnect structure having enhanced performance and reliability
US9190316B2 (en) * 2011-10-26 2015-11-17 Globalfoundries U.S. 2 Llc Low energy etch process for nitrogen-containing dielectric layer
US9269612B2 (en) * 2011-11-22 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of forming damascene interconnect structures
US8994178B2 (en) * 2012-03-29 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method for forming the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102157441A (zh) * 2007-04-25 2011-08-17 联华电子股份有限公司 复合覆盖层的制作方法

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