JP2009267068A - チップの実装方法 - Google Patents
チップの実装方法 Download PDFInfo
- Publication number
- JP2009267068A JP2009267068A JP2008114633A JP2008114633A JP2009267068A JP 2009267068 A JP2009267068 A JP 2009267068A JP 2008114633 A JP2008114633 A JP 2008114633A JP 2008114633 A JP2008114633 A JP 2008114633A JP 2009267068 A JP2009267068 A JP 2009267068A
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- JP
- Japan
- Prior art keywords
- layer
- chip
- substrate
- led chip
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
【解決手段】チップたるLEDチップ1の実装面側(裏面側)に共晶組成付近の第1のAuSn層12aを形成するとともに被搭載部材たるベース基板20の実装面側にAu層13を形成してから、LEDチップ1の実装面側の第1のAuSn層12aとステージ110の上面側に配置されたベース基板20のAu層13とを対向させ、第1のAuSn層12aとAu層13とを接触させてから、LEDチップ1側からの加圧および加熱により第1のAuSn層12aとAu層13とを溶融させて等温凝固させ、減圧および冷却を行うことで第1のAuSn層12aよりもAuの組成比が高く且つ高融点の第2のAuSn層からなる接合部15を形成する接合工程を行う。
【選択図】 図1
Description
11 下地層
12a 第1のAuSn層
13 Au層
15 接合部
20 ベース基板(被搭載部材)
25aa ダイパッド部
100 チップ吸着ツール
Claims (2)
- チップの実装面側に第1のAuSn層を形成するAuSn層形成工程および被搭載部材の実装面側にAu層を形成するAu層形成工程を含む接合前工程と、接合前工程の後で被搭載部材の実装面側のAu層とチップの実装面側の第1のAuSn層とを接触させてチップ側からの加圧および加熱により第1のAuSn層とAu層とを溶融させて等温凝固させることで第1のAuSn層よりもAuの組成比が高く且つ高融点の第2のAuSn層からなる接合部を形成する接合工程とを備えることを特徴とするチップの実装方法。
- 接合前工程では、AuSn層形成工程において第1のAuSn層として共晶組成付近のAuSn層を形成するようにし、第2のAuSn層におけるAuの組成比が90at%を下回らないように第1のAuSn層およびAu層それぞれの膜厚を設定することを特徴とする請求項1記載のチップの実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008114633A JP2009267068A (ja) | 2008-04-24 | 2008-04-24 | チップの実装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008114633A JP2009267068A (ja) | 2008-04-24 | 2008-04-24 | チップの実装方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009267068A true JP2009267068A (ja) | 2009-11-12 |
Family
ID=41392540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008114633A Pending JP2009267068A (ja) | 2008-04-24 | 2008-04-24 | チップの実装方法 |
Country Status (1)
Country | Link |
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JP (1) | JP2009267068A (ja) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003200289A (ja) * | 2001-09-27 | 2003-07-15 | Furukawa Electric Co Ltd:The | 部材の接合方法、その方法で得られた接合部材 |
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2008
- 2008-04-24 JP JP2008114633A patent/JP2009267068A/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003200289A (ja) * | 2001-09-27 | 2003-07-15 | Furukawa Electric Co Ltd:The | 部材の接合方法、その方法で得られた接合部材 |
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