JP2009231322A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2009231322A
JP2009231322A JP2008071321A JP2008071321A JP2009231322A JP 2009231322 A JP2009231322 A JP 2009231322A JP 2008071321 A JP2008071321 A JP 2008071321A JP 2008071321 A JP2008071321 A JP 2008071321A JP 2009231322 A JP2009231322 A JP 2009231322A
Authority
JP
Japan
Prior art keywords
chip
leads
lead
plating layer
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008071321A
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English (en)
Japanese (ja)
Other versions
JP2009231322A5 (https=
Inventor
Akihiko Kameoka
昭彦 亀岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2008071321A priority Critical patent/JP2009231322A/ja
Publication of JP2009231322A publication Critical patent/JP2009231322A/ja
Publication of JP2009231322A5 publication Critical patent/JP2009231322A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP2008071321A 2008-03-19 2008-03-19 半導体装置の製造方法 Pending JP2009231322A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008071321A JP2009231322A (ja) 2008-03-19 2008-03-19 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008071321A JP2009231322A (ja) 2008-03-19 2008-03-19 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2009231322A true JP2009231322A (ja) 2009-10-08
JP2009231322A5 JP2009231322A5 (https=) 2011-03-03

Family

ID=41246440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008071321A Pending JP2009231322A (ja) 2008-03-19 2008-03-19 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP2009231322A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012074495A (ja) * 2010-09-28 2012-04-12 Dainippon Printing Co Ltd 半導体装置
US9263374B2 (en) 2010-09-28 2016-02-16 Dai Nippon Printing Co., Ltd. Semiconductor device and manufacturing method therefor
JP2018117009A (ja) * 2017-01-17 2018-07-26 株式会社三井ハイテック リードフレームの製造方法およびリードフレーム

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818947A (ja) * 1981-07-27 1983-02-03 Toshiba Corp リ−ドフレ−ム
JPS61292928A (ja) * 1985-06-21 1986-12-23 Hitachi Ltd 半導体装置
JPS62145754A (ja) * 1985-12-20 1987-06-29 Hitachi Ltd 半導体装置
JPH03185855A (ja) * 1989-12-15 1991-08-13 Mitsui High Tec Inc リードフレームの製造方法
JPH0982870A (ja) * 1995-09-14 1997-03-28 Toshiba Corp 半導体装置、リードフレーム及びその製造方法
JPH09219486A (ja) * 1996-02-08 1997-08-19 Toppan Printing Co Ltd リードフレーム
JP2002329829A (ja) * 1992-03-27 2002-11-15 Hitachi Ltd 半導体集積回路装置およびその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818947A (ja) * 1981-07-27 1983-02-03 Toshiba Corp リ−ドフレ−ム
JPS61292928A (ja) * 1985-06-21 1986-12-23 Hitachi Ltd 半導体装置
JPS62145754A (ja) * 1985-12-20 1987-06-29 Hitachi Ltd 半導体装置
JPH03185855A (ja) * 1989-12-15 1991-08-13 Mitsui High Tec Inc リードフレームの製造方法
JP2002329829A (ja) * 1992-03-27 2002-11-15 Hitachi Ltd 半導体集積回路装置およびその製造方法
JPH0982870A (ja) * 1995-09-14 1997-03-28 Toshiba Corp 半導体装置、リードフレーム及びその製造方法
JPH09219486A (ja) * 1996-02-08 1997-08-19 Toppan Printing Co Ltd リードフレーム

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012074495A (ja) * 2010-09-28 2012-04-12 Dainippon Printing Co Ltd 半導体装置
US9263374B2 (en) 2010-09-28 2016-02-16 Dai Nippon Printing Co., Ltd. Semiconductor device and manufacturing method therefor
JP2018117009A (ja) * 2017-01-17 2018-07-26 株式会社三井ハイテック リードフレームの製造方法およびリードフレーム

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