JP2009193927A - Chip fuse and its manufacturing method - Google Patents

Chip fuse and its manufacturing method Download PDF

Info

Publication number
JP2009193927A
JP2009193927A JP2008036191A JP2008036191A JP2009193927A JP 2009193927 A JP2009193927 A JP 2009193927A JP 2008036191 A JP2008036191 A JP 2008036191A JP 2008036191 A JP2008036191 A JP 2008036191A JP 2009193927 A JP2009193927 A JP 2009193927A
Authority
JP
Japan
Prior art keywords
heat storage
storage layer
fuse
film
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008036191A
Other languages
Japanese (ja)
Other versions
JP4612066B2 (en
Inventor
Katsuya Yamagishi
克哉 山岸
Hideki Kiyono
英樹 清野
Hitoshi Sato
仁 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kamaya Electric Co Ltd
Original Assignee
Kamaya Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kamaya Electric Co Ltd filed Critical Kamaya Electric Co Ltd
Priority to JP2008036191A priority Critical patent/JP4612066B2/en
Priority to CN2008800004128A priority patent/CN101636808B/en
Priority to KR1020087023427A priority patent/KR101050243B1/en
Priority to PCT/JP2008/053550 priority patent/WO2009104279A1/en
Priority to TW098105128A priority patent/TWI391974B/en
Publication of JP2009193927A publication Critical patent/JP2009193927A/en
Application granted granted Critical
Publication of JP4612066B2 publication Critical patent/JP4612066B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02—Details
    • H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/05—Component parts thereof
    • H01H85/055—Fusible members
    • H01H85/08—Fusible members characterised by the shape or form of the fusible member
    • H01H85/10—Fusible members characterised by the shape or form of the fusible member with constriction for localised fusing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H69/00—Apparatus or processes for the manufacture of emergency protective devices
    • H01H69/02—Manufacture of fuses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/0039—Means for influencing the rupture process of the fusible element
    • H01H85/0047—Heating means
    • H01H85/006—Heat reflective or insulating layer on the casing or on the fuse support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/0039—Means for influencing the rupture process of the fusible element
    • H01H85/0047—Heating means
    • H01H85/0065—Heat reflective or insulating layer on the fusible element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02—Details
    • H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/0411—Miniature fuses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02—Details
    • H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/046—Fuses formed as printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02—Details
    • H01H85/0241—Structural association of a fuse and another component or apparatus
    • H01H2085/0283—Structural association with a semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02—Details
    • H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/0411—Miniature fuses
    • H01H2085/0414—Surface mounted fuses

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip fuse without freedom of pre-arcing characteristics restricted, preventing pre-arcing time at high magnification from getting short against the rated current, and for shortening a pre-arcing time at low magnification against the rated current. <P>SOLUTION: The chip fuse 10 is so structured that a first heat storage layer 12 made of a film material with low thermal conductivity is formed on an insulation board 11, a fuse film 13 is formed on the first heat storage layer 12 so as not to come in contact with the insulation board 11. The fuse film 13 includes a fuse element part 13b between front electrode parts 13a arranged at either end of the fuse film, and a second heat storage layer 15 made of a film material with low thermal conductivity is formed on the fuse element part 13b, with the first heat storage layer 12 made thicker than the second heat storage layer 15. The first heat storage layer 12 and the second heat storage layer 15 are formed of a sheet-shaped material of a B-stage state containing a photosensitive group. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、チップヒューズ及びその製造方法に関し、さらに詳細には、熱伝導性の低い膜によりヒューズ要素部の上層及び下層とが形成されてなるチップヒューズ及びその製造方法に関する。   The present invention relates to a chip fuse and a manufacturing method thereof, and more particularly to a chip fuse in which an upper layer and a lower layer of a fuse element portion are formed of a film having low thermal conductivity and a manufacturing method thereof.

チップヒューズに関して既に開示されている技術としては、特許文献１に記載されたものがある。これは、無機質の基板の上面にシリコーン樹脂膜を形成し、このシリコーン樹脂膜の上にヒューズ膜を形成し、さらに、ヒューズ膜の上にシリコーン樹脂により保護膜を形成したチップヒューズに関するものであり、基板上面のシリコーン樹脂膜の厚さとして、１０μｍが例示されている。
この特許文献１では、シリコーン樹脂を使用することにより、プリント配線板との接続部のはんだの溶融、発火を阻止することが述べられているが、ヒューズエレメントの材料及び伝熱面積等を変えても、溶断特性の自由度が制限されてしまう課題は残される。 As a technique already disclosed regarding the chip fuse, there is one described in Patent Document 1. This relates to a chip fuse in which a silicone resin film is formed on the top surface of an inorganic substrate, a fuse film is formed on the silicone resin film, and a protective film is formed on the fuse film with a silicone resin. The thickness of the silicone resin film on the upper surface of the substrate is exemplified as 10 μm.
In this patent document 1, it is described that the use of silicone resin prevents melting and ignition of solder at the connection portion with the printed wiring board. However, the material and heat transfer area of the fuse element are changed. However, the subject that the freedom degree of a fusing characteristic will be restrict | limited is left.

これ以外にも、チップヒューズを製造する方法に関する特許文献２には、ヒューズエレメントの発熱量と周りの部材への放熱量とのバランスにより、溶断するまでの温度上昇が決定し、溶断時間が決まることが記載されている。そして、この溶断時間に影響する因子は、抵抗値、伝熱面積、熱伝達率であり、抵抗値は発熱量に対する因子であり、さらに、伝熱面積と熱伝達率は放熱量に対する因子であり、チップヒューズの溶断特性の自由度を上げるためには、これらの因子について検討する必要がある旨が記載されている。
しかしながら、この特許文献２では、ヒューズエレメント周りの部材の材質や伝熱面積については、具体的に検討されておらず、ヒューズエレメントから周りの部材への放熱量を制御する手段や方法についても示されていない。
特開平１１−９６８８６号公報 特開平９−３２０４４５号公報 In addition to this, in Patent Document 2 relating to a method of manufacturing a chip fuse, the temperature rise until fusing is determined and the fusing time is determined by the balance between the heat generation amount of the fuse element and the heat dissipation amount to the surrounding members. It is described. The factors affecting the fusing time are the resistance value, the heat transfer area, and the heat transfer rate. The resistance value is a factor for the heat generation amount. Further, the heat transfer area and the heat transfer rate are factors for the heat release amount. It is described that these factors need to be examined in order to increase the degree of freedom of the fusing characteristics of the chip fuse.
However, this Patent Document 2 does not specifically examine the material and heat transfer area of the members around the fuse element, and also shows means and methods for controlling the heat radiation from the fuse element to the surrounding members. It has not been.
JP-A-11-96886 Japanese Patent Laid-Open No. 9-320445

本発明は、上記課題を解決するものであり、その目的は、溶断特性の自由度が制限されず、定格電流に対して高倍率での溶断時間が短くなることを防止すると共に、定格電流に対する低倍率での溶断時間を短くすることが可能なチップヒューズ及びその製造方法を提供することである。
また本発明は、上述のようなチップヒューズを精度良く、且つ比較的容易に形成することが可能なチップヒューズの製造方法を提供することである。 The present invention solves the above-mentioned problems, and its purpose is not to limit the degree of freedom of the fusing characteristics, and to prevent the fusing time at a high magnification relative to the rated current from being shortened, and to the rated current. A chip fuse capable of shortening a fusing time at a low magnification and a manufacturing method thereof.
It is another object of the present invention to provide a chip fuse manufacturing method capable of forming the above-described chip fuse with high accuracy and relatively easily.

本発明では、以下に記載する（１）乃至（３）の手段により、上記課題が解決される。   In the present invention, the above problems are solved by means (1) to (3) described below.

（１）熱伝導性の低い膜材料からなる第一の蓄熱層が絶縁基板上に形成され、当該第一の蓄熱層の上に絶縁基板に接触しないようにヒューズ膜が形成され、当該ヒューズ膜は両端に配置される表電極部の間にヒューズ要素部を有するものであり、当該ヒューズ要素部の上に熱伝導性の低い膜材料からなる第二の蓄熱層が形成され、前記第一の蓄熱層が前記第二の蓄熱層よりも厚く形成されたものであるチップヒューズ。   (1) A first heat storage layer made of a film material having low thermal conductivity is formed on an insulating substrate, a fuse film is formed on the first heat storage layer so as not to contact the insulating substrate, and the fuse film Has a fuse element part between front electrode parts arranged at both ends, a second heat storage layer made of a film material having low thermal conductivity is formed on the fuse element part, and the first element A chip fuse in which the heat storage layer is formed thicker than the second heat storage layer.

（２）熱伝導性の低い膜材料からなる前記第一の蓄熱層及び前記第二の蓄熱層が、感光基を含有するＢステージ状態（半硬化状態）のシート状材料から形成されたものである前記（１）に記載のチップヒューズ。   (2) The first heat storage layer and the second heat storage layer made of a film material having low thermal conductivity are formed from a sheet-like material in a B stage state (semi-cured state) containing a photosensitive group. The chip fuse according to (1) above.

（３）絶縁基板上に第一の蓄熱層が形成され、第一の蓄熱層の上にヒューズ膜が形成され、ヒューズ膜は両端に配置される表電極部の間にヒューズ要素部を有し、ヒューズ要素部の上に第二の蓄熱層が形成されるチップヒューズの製造方法であって、感光基を含有し、ほぼ均一の厚さに形成されたＢステージ状態（半硬化状態）のシート状材料を絶縁基板上に所定枚数重畳して第一の蓄熱層を形成する工程と、絶縁基板に接触しないように第一の蓄熱層の上にヒューズ膜を形成するとともに、表電極部の間にヒューズ要素部を形成する工程と、前記第一の蓄熱層に使用した同じＢステージ状態のシート状材料を両表電極部間に所定枚数重畳して第二の蓄熱層を形成する工程とを含み、前記第一の蓄熱層の形成工程では、前記第二の蓄熱層の形成工程よりも、重畳するＢステージ状態のシート状材料の枚数を多くすることを特徴とするチップヒューズの製造方法。   (3) A first heat storage layer is formed on an insulating substrate, a fuse film is formed on the first heat storage layer, and the fuse film has a fuse element portion between front electrode portions disposed at both ends. A method for manufacturing a chip fuse in which a second heat storage layer is formed on a fuse element portion, and a sheet in a B stage state (semi-cured state) containing a photosensitive group and having a substantially uniform thickness Forming a first heat storage layer by overlapping a predetermined number of sheet-like materials on an insulating substrate, forming a fuse film on the first heat storage layer so as not to contact the insulating substrate, and between the surface electrode portions Forming a fuse element portion and a step of forming a second heat storage layer by superposing a predetermined number of the same B-stage sheet-like material used for the first heat storage layer between both surface electrode portions. Including, in the step of forming the first heat storage layer, the shape of the second heat storage layer Than method of manufacturing an Fuses, characterized in that to increase the number of sheet-like material of B-stage to be superimposed.

本発明において、第一の蓄熱層及び第二の蓄熱層を構成する熱伝導性の低い膜材料は、熱伝導率が０．１〜０．４Ｗ／ｍ℃程度の膜材料であることが好ましく、例えば、アクリレート樹脂、エポキシ樹脂等の樹脂材料及び感光基を含有するシート状材料を使用して形成することが可能である。   In the present invention, the low thermal conductivity film material constituting the first heat storage layer and the second heat storage layer is preferably a film material having a thermal conductivity of about 0.1 to 0.4 W / m ° C. For example, it can be formed by using a resin material such as an acrylate resin or an epoxy resin and a sheet-like material containing a photosensitive group.

本発明のチップヒューズは、熱伝導性の低い膜材料からなる蓄熱層をそれぞれヒューズ膜の上下に設け、下層の蓄熱層を上層の蓄熱層よりも厚く形成したものであるため、溶断特性の自由度が制限されず、定格電流に対して高倍率での溶断時間が短くなることを防止し、定格電流に対する低倍率での溶断時間を短くすることが可能になった。
すなわち、チップヒューズに通電してヒューズ要素部の温度が上昇すると、その熱は下方に伝わり第一の蓄熱層に蓄えられ、一方、上方に伝わった熱は第二の蓄熱層に蓄えられる。一般的に、絶縁基板の方が空気よりも熱伝導率が高いものであるため、第一の蓄熱層を第二の蓄熱層よりも厚く形成することにより、第一の蓄熱層から絶縁基板を介して下方に逃げる熱を抑制し、これにより熱量の少ない低倍率では熱を閉じ込めることによって溶断時間を短くすることが可能になった。また第一の蓄熱層よりも比較的薄く形成された第二の蓄熱層により、熱量の多い高倍率では熱を放出することによって溶断時間が短くなることの防止が可能になった。 In the chip fuse of the present invention, heat storage layers made of a film material having low thermal conductivity are provided on the upper and lower sides of the fuse film, respectively, and the lower heat storage layer is formed thicker than the upper heat storage layer. The degree is not limited, and it is possible to prevent the fusing time at a high magnification with respect to the rated current from being shortened, and to shorten the fusing time at a low magnification with respect to the rated current.
That is, when the chip fuse is energized and the temperature of the fuse element rises, the heat is transferred downward and stored in the first heat storage layer, while the heat transferred upward is stored in the second heat storage layer. Generally, since the insulating substrate has a higher thermal conductivity than air, the insulating substrate is formed from the first heat storage layer by forming the first heat storage layer thicker than the second heat storage layer. Therefore, it is possible to shorten the fusing time by confining the heat at a low magnification with a small amount of heat. Further, the second heat storage layer formed relatively thinner than the first heat storage layer can prevent the fusing time from being shortened by releasing heat at a high magnification with a large amount of heat.

また本発明のチップヒューズの製造方法では、絶縁基板上にほぼ均一の厚さに形成されたＢステージ状態のシート状材料を所定枚数重畳して第一の蓄熱層を形成し、この第一の蓄熱層上に設けたヒューズ膜の上に、さらに同じＢステージ状態のシート状材料を所定枚数重畳して第二の蓄熱層を形成する。これらシート状材料は、その厚さが均一性に富むものであるため、第一及び第二の蓄熱層を所望の厚さに精度良く且つ比較的容易に形成することができる。   In the chip fuse manufacturing method of the present invention, a first heat storage layer is formed by overlapping a predetermined number of B-staged sheet-like materials formed on an insulating substrate with a substantially uniform thickness. A second heat storage layer is formed on the fuse film provided on the heat storage layer by further overlapping a predetermined number of sheet materials in the same B stage state. Since these sheet-like materials are rich in thickness, the first and second heat storage layers can be accurately and relatively easily formed to a desired thickness.

以下、図面を参照して本発明の一実施形態について説明するが、本発明はこれに限定されるものではない。   Hereinafter, although one embodiment of the present invention is described with reference to drawings, the present invention is not limited to this.

図１（ａ）〜（ｄ）及び図２（ｅ）〜（ｈ）は本発明のチップヒューズ１０を製造する工程を示した平面図であり、図３（ａ）は図２（ｈ）のＡ−Ａ線、図３（ｂ）は図２（ｈ）のＢ−Ｂ線におけるチップヒューズ１０の断面図である。
チップヒューズ１０は、絶縁基板１１の上に熱伝導性の低い膜材料からなる第一の蓄熱層１２が形成され、第一の蓄熱層１２の上にヒューズ膜１３が設けられ、ヒューズ膜１３は、両端に配置された表電極部１３ａと、これら両端の表電極部１３ａを接続するように比較的狭い幅で形成されたヒューズ要素部１３ｂとを有し、表電極部１３ａの一部分とヒューズ要素部１３ｂの全面とにＮｉとＳｎめっき膜またはＳｎめっき膜が形成され、このめっき膜が溶断部１４となる。さらに、溶断部１４の上には、溶断部１４よりも若干広い領域に熱伝導性の低い膜材料からなる第二の蓄熱層１５が設けられ、第二の蓄熱層１５の上に保護層１６が形成され、絶縁基板１１の裏側の両端に裏電極１７が設けられ、絶縁基板１１の両端面に端面電極１８が設けられ、電極めっき膜１９が表電極１３ａ、端面電極１８及び裏電極１７を覆うように設けられる。 1 (a) to 1 (d) and FIGS. 2 (e) to (h) are plan views showing steps of manufacturing the chip fuse 10 of the present invention, and FIG. 3 (a) is a plan view of FIG. 2 (h). FIG. 3B is a cross-sectional view of the chip fuse 10 taken along the line BB in FIG. 2H.
In the chip fuse 10, a first heat storage layer 12 made of a film material having low thermal conductivity is formed on an insulating substrate 11, a fuse film 13 is provided on the first heat storage layer 12, and the fuse film 13 is And a front electrode portion 13a arranged at both ends, and a fuse element portion 13b formed with a relatively narrow width so as to connect the front electrode portions 13a at both ends, and a part of the front electrode portion 13a and a fuse element Ni and Sn plating film or Sn plating film is formed on the entire surface of the portion 13 b, and this plating film becomes the fusing part 14. Further, a second heat storage layer 15 made of a film material having low thermal conductivity is provided on the fusing part 14 in a slightly larger area than the fusing part 14, and the protective layer 16 is provided on the second heat storage layer 15. The back electrode 17 is provided on both ends of the back side of the insulating substrate 11, the end face electrodes 18 are provided on both end faces of the insulating substrate 11, and the electrode plating film 19 connects the front electrode 13 a, the end face electrode 18, and the back electrode 17. It is provided to cover.

ここで、絶縁基板１１としてはアルミナ基板を使用し、また第一の蓄熱層１２及び第二の蓄熱層１５は、アクリレート樹脂、エポキシ樹脂等の樹脂材料及び感光基を含有する厚さ３０μｍ程度のＢステージ状態（半硬化状態）のシート状材料をそれぞれ所定枚数使用して形成する。例えば、第一の蓄熱層１２はＢステージ状態のシート状材料を二枚重ね合わせ、第二の蓄熱層１５は同じＢステージ状態のシート状材料を一枚使用して形成する。このＢステージ状態の材料を硬化したシート状材料はエッチング液に対する耐薬品性に優れ、且つ熱伝導性の低いものである。
第一の蓄熱層１２は、絶縁基板１１の一次分割溝１１ａと２次分割溝１１ｂとの所定箇所を除いて、絶縁基板１１のほぼ全面を被覆するものであり、この第一の蓄熱層１２が除去された除去部１２ａは、図１（ｂ）（ｃ）に示したような形状及び配置、すなわち、一次分割溝１１ａと２次分割溝１１ｂとの所定長を跨いで、これら分割溝１１ａ，１１ｂから離間するように形成される。ヒューズ膜１３は、絶縁基板１１に接触しないように、図１（ｄ）に示したような形状で第一の蓄熱層１２の上に積層される。 Here, an alumina substrate is used as the insulating substrate 11, and the first heat storage layer 12 and the second heat storage layer 15 have a thickness of about 30 μm containing a resin material such as an acrylate resin or an epoxy resin and a photosensitive group. A predetermined number of B-stage (semi-cured) sheet materials are used. For example, the first heat storage layer 12 is formed by superimposing two B-stage sheet materials, and the second heat storage layer 15 is formed using one sheet of the same B-stage sheet material. The sheet-like material obtained by curing the B-stage material is excellent in chemical resistance against the etchant and has low thermal conductivity.
The first heat storage layer 12 covers almost the entire surface of the insulating substrate 11 except for the predetermined portions of the primary dividing grooves 11a and the secondary dividing grooves 11b of the insulating substrate 11, and the first heat storage layer 12 The removed portion 12a from which the slag has been removed has a shape and arrangement as shown in FIGS. 1B and 1C, that is, spans a predetermined length between the primary divided groove 11a and the secondary divided groove 11b, and these divided grooves 11a. , 11b. The fuse film 13 is laminated on the first heat storage layer 12 in a shape as shown in FIG. 1D so as not to contact the insulating substrate 11.

以上のように第一の蓄熱層１２を第二の蓄熱層１５よりも厚く、例えば、ほぼ２倍の厚さで形成することにより、溶断特性の自由度が制限されず、定格電流に対して高倍率での溶断時間が短くなることを防止し、定格電流に対する低倍率での溶断時間を短くすることが可能になる。   As described above, by forming the first heat storage layer 12 thicker than the second heat storage layer 15, for example, approximately twice the thickness, the degree of freedom of the fusing characteristics is not limited, and the rated current It is possible to prevent the fusing time at a high magnification from being shortened and to shorten the fusing time at a low magnification with respect to the rated current.

次に、定格電流１Ａのチップヒューズ１０の製造方法について、図１及び図２を参照して説明する。チップヒューズを製造するための集合絶縁基板として、アルミナの純度が９６％程度のアルミナ基板を使用する。チップヒューズ１０は、集合絶縁基板の上に複数層にわたり各構成を形成し、縦方向、横方向に切断することにより製造するものであるが、図１（ａ）（ｂ）では集合絶縁基板上の複数区画を示し、図１（ｃ）（ｄ）及び図２（ｅ）〜（ｈ）では集合絶縁基板上の一区画、すなわち、一つのチップヒューズの平面図を示した。   Next, a manufacturing method of the chip fuse 10 having a rated current of 1A will be described with reference to FIGS. An alumina substrate having an alumina purity of about 96% is used as a collective insulating substrate for manufacturing a chip fuse. The chip fuse 10 is manufactured by forming each component over a plurality of layers on a collective insulating substrate and cutting in the vertical and horizontal directions. In FIGS. 1 (a) and 1 (b), the chip fuse 10 is formed on the collective insulating substrate. 1 (c), (d) and FIGS. 2 (e) to 2 (h), one section on the collective insulating substrate, that is, a plan view of one chip fuse is shown.

［集合絶縁基板の溝刻設工程］
最初に、レーザー等の手段により集合絶縁基板１１に切断用の一次分割溝１１ａと二次分割溝１１ｂとを刻設する。集合絶縁基板には、予め一次分割溝１１ａと二次分割溝１１ｂとが形成されたものもあり、このような集合絶縁基板を使用する場合には、溝の刻設工程は省かれる。 [Groove-cutting process for collective insulating substrate]
First, a primary dividing groove 11a and a secondary dividing groove 11b for cutting are formed on the collective insulating substrate 11 by means of a laser or the like. Some collective insulating substrates have primary division grooves 11a and secondary division grooves 11b formed in advance, and when such collective insulation substrates are used, the step of forming grooves is omitted.

［第一の蓄熱層の形成工程］
第一の蓄熱層１２を形成するため、絶縁基板１１上に所定枚数のシート状材料を貼り付ける。シート状材料は、アクリレート樹脂、エポキシ樹脂などの樹脂材料及び感光基を含み、厚さ３０μｍ程度に形成されたＢステージ状態のものを使用する。貼り付け工程は、このＢステージ状態のシート状材料の一枚を絶縁基板１１上に貼り付け、所定温度に加熱し、所定圧力で加圧した後に、さらに、もう一枚のシート状材料をその上に同様に加熱しながら加圧して貼り重ねる。加熱、加圧された二枚のシート状材料は接着後に厚さ５６μｍ程度になる。このように、Ｂステージ状態のシート状材料を所定枚数だけ重ね合わせることにより、第一の蓄熱層１２の厚さを高い精度で調整することができる。
次に、シート状材料の上にフォトマスクを介して紫外線５００ｍＪ／ｃｍ2で露光した後、炭酸ナトリウム溶液１ｗｔ％に数分間浸漬し、シート状材料を、図１（ｂ）（ｃ）に示した形状に形成する。これにより、第一の蓄熱層１２が除去された除去部１２ａが絶縁基板１１上に形成される。
上述のように、シート状材料として感光基を含むものを使用すれば、第一の蓄熱層１２の平面形状の寸法精度が高まり、溶断特性のばらつきを低減することができる。 [Formation process of first heat storage layer]
In order to form the first heat storage layer 12, a predetermined number of sheet-like materials are bonded onto the insulating substrate 11. The sheet-like material includes a resin material such as an acrylate resin and an epoxy resin, and a photosensitive group, and a B-stage material formed to a thickness of about 30 μm is used. In the pasting step, one sheet-like material in the B-stage state is pasted on the insulating substrate 11, heated to a predetermined temperature and pressurized with a predetermined pressure, and then another sheet-like material is further added to the sheet-like material. In the same manner, pressurize and laminate while heating. The two sheet-like materials heated and pressurized have a thickness of about 56 μm after bonding. As described above, the thickness of the first heat storage layer 12 can be adjusted with high accuracy by overlapping a predetermined number of sheets of the B-stage state sheet material.
Next, the sheet-like material is exposed to ultraviolet rays of 500 mJ / cm 2 through a photomask and then immersed in 1 wt% of a sodium carbonate solution for several minutes. The sheet-like material is shown in FIGS. 1B and 1C. Formed into a different shape. Thereby, the removal part 12a from which the 1st thermal storage layer 12 was removed is formed on the insulating substrate 11. FIG.
As described above, when a sheet-like material containing a photosensitive group is used, the dimensional accuracy of the planar shape of the first heat storage layer 12 can be increased, and variations in fusing characteristics can be reduced.

［ヒューズ膜の形成工程］
第一の蓄熱層１２を形成した絶縁基板１１上に厚さがほぼ３μｍ程度の電解銅箔又は圧延銅箔を貼り付ける。この貼り付け工程は、常温よりも高い温度で所定圧力を所定時間加えることにより行われる。次に、電解銅箔の上にネガタイプのドライフィルムを貼るか、又は液状のレジストを塗布し、その上からフォトマスクを介して露光した後、電解銅箔をエッチングしてドライフィルム又は液状レジストを剥離させる。以上のような工程により、ヒューズ膜１３を図１（ｄ）に示したような平面形状に形成する。 [Fuse film formation process]
An electrolytic copper foil or a rolled copper foil having a thickness of about 3 μm is pasted on the insulating substrate 11 on which the first heat storage layer 12 is formed. This attaching step is performed by applying a predetermined pressure for a predetermined time at a temperature higher than room temperature. Next, a negative type dry film is applied on the electrolytic copper foil, or a liquid resist is applied and exposed through a photomask, and then the electrolytic copper foil is etched to form a dry film or a liquid resist. Remove. Through the steps as described above, the fuse film 13 is formed in a planar shape as shown in FIG.

［ヒューズ膜溶断部の形成工程］
ヒューズ膜１３におけるヒューズ要素部１３ｂの全面と、この両側に連続する表電極部１３ａの一部分には、電気めっき法により、ＮｉとＳｎめっき膜またはＳｎめっき膜を設けることで、図２（ｅ）に示したような溶断部１４を形成し、これによりヒューズ膜１３にＭ効果を与えて溶断特性を得る。 [Process for forming fuse film melted part]
2E is formed by providing Ni and Sn plating film or Sn plating film on the entire surface of the fuse element part 13b in the fuse film 13 and a part of the surface electrode part 13a continuous on both sides by electroplating. The fusing part 14 as shown in FIG. 5 is formed, thereby giving an M effect to the fuse film 13 to obtain fusing characteristics.

［第二の蓄熱層の形成工程］
次に、図２（ｆ）に示したように、溶断部１４を全て覆う範囲に第二の蓄熱層１５を形成する。第二の蓄熱層１５も、第一の蓄熱層１２と同じ厚さ３０μｍ程度に形成されたＢステージ状態のシート状材料を使用し、このシート状材料の一枚を集合絶縁基板１１の全域に貼り付け、所定温度に加熱しながら所定圧力で接着する。この一枚のシート状材料は接着後に厚さ２５μｍ程度になる。接着したシート状材料にはフォトマスクを介して紫外線を露光し、その後に、炭酸ナトリウム溶液に数分間浸漬し、図１（ｇ）に示した形状に形成する。 [Second heat storage layer forming step]
Next, as shown in FIG. 2 (f), the second heat storage layer 15 is formed in a range that covers the entire fusing part 14. The second heat storage layer 15 also uses a B-stage sheet-like material formed to the same thickness as the first heat storage layer 12 and has a thickness of about 30 μm. Adhering and bonding at a predetermined pressure while heating to a predetermined temperature. This single sheet material has a thickness of about 25 μm after bonding. The adhered sheet-like material is exposed to ultraviolet rays through a photomask, and then immersed in a sodium carbonate solution for several minutes to form the shape shown in FIG.

［保護層の形成工程］
次に、第二の蓄熱層１５を全て覆うように、これより若干広い範囲に保護層１６を形成する。保護層１６は、スクリーン印刷によりエポキシ系樹脂材料から形成される膜であり、これにより隠蔽性や機械的強度が高められる。 [Protective layer forming step]
Next, the protective layer 16 is formed in a slightly wider range so as to cover the entire second heat storage layer 15. The protective layer 16 is a film formed from an epoxy-based resin material by screen printing, which improves the concealability and mechanical strength.

［裏電極、端面電極等の形成工程］
保護層１６を形成した後に、絶縁基板１１の裏側にスクリーン印刷法で銀ペーストを塗布して焼き付け、裏電極１７を形成する。次に、集合絶縁基板を一次分割溝１１ａに沿って切断して短冊状の基板を形成し、この短冊状基板の長辺方向の側面に銀ペーストを塗布して焼き付けること、またはスパッタ法により、Ｃｒ膜とＮｉ膜を成膜することにより端
面電極１８を形成する。さらに、短冊状の基板を２次分割溝１１ｂに沿って切断し、一個ずつのチップ形状とし、バレルめっき法により、Ｃｕ膜、Ｎｉ膜及びＳｎ膜からなる電極めっき膜１９を順次形成すれば、図２（ｈ）及び図３に示したように、本発明のチップヒューズ１０が完成する。 [Back electrode, end face electrode formation process]
After forming the protective layer 16, a silver paste is applied to the back side of the insulating substrate 11 by screen printing and baked to form the back electrode 17. Next, the aggregated insulating substrate is cut along the primary dividing grooves 11a to form a strip-shaped substrate, and a silver paste is applied to the side surface in the long side direction of the strip-shaped substrate and baked, or by sputtering. The end face electrode 18 is formed by forming a Cr film and a Ni film. Furthermore, if the strip-shaped substrate is cut along the secondary dividing grooves 11b to form chips one by one, and the electrode plating film 19 made of Cu film, Ni film, and Sn film is sequentially formed by barrel plating, As shown in FIGS. 2 (h) and 3, the chip fuse 10 of the present invention is completed.

次に、図４は、本発明の一実施形態である定格電流１Ａのチップヒューズと、比較例のチップヒューズとの溶断特性を比較したグラフである。図５は図４における定格電流比が低い範囲を拡大したグラフであり、図６は図４における定格電流比が高い範囲を拡大したグラフである。
ここで、サンプルＣは本発明の一実施形態であり、第一の蓄熱層がほぼ６０μｍ、第二の蓄熱層がほぼ３０μｍに形成されたものである。
一方、サンプルＡ，Ｂ，Ｄのチップヒューズは比較例であり、何れのサンプルも、第一の蓄熱層と第二の蓄熱層との相対的な厚さの関係が本発明によるチップヒューズとは異なるものであるが、これ以外の構成は本発明のチップヒューズと同様に形成されたものである。サンプルＡは第一の蓄熱層がほぼ３０μｍ、第二の蓄熱層がほぼ３０μｍに形成されたものである。サンプルＢは第一の蓄熱層がほぼ３０μｍ、第二の蓄熱層がほぼ６０μｍに形成されたものである。サンプルＤは第一の蓄熱層がほぼ６０μｍ、第二の蓄熱層がほぼ６０μｍに形成されたものである。
本発明の一実施形態であるサンプルＣと、サンプルＤ（第一の蓄熱層がサンプルＣと同じ厚さ）とを比較すると、定格電流比が低い範囲では、図５に示したように、サンプルＣのほうがサンプルＤよりも溶断時間が短い。一方、定格電流比が高い範囲では、図６に示したように、サンプルＣのほうがサンプルＤよりも溶断時間が長い。このことから、本発明のチップヒューズは、定格電流に対して高倍率での溶断時間が短くなることを防止し、定格電流に対する低倍率での溶断時間を短くすることが可能になることが分かる。 Next, FIG. 4 is a graph comparing the fusing characteristics of a chip fuse having a rated current of 1A according to an embodiment of the present invention and a chip fuse of a comparative example. FIG. 5 is a graph in which the range in which the rated current ratio is low in FIG. 4 is enlarged, and FIG. 6 is a graph in which the range in which the rated current ratio is high in FIG.
Here, Sample C is an embodiment of the present invention, in which the first heat storage layer is formed to be approximately 60 μm and the second heat storage layer is formed to be approximately 30 μm.
On the other hand, the chip fuses of Samples A, B, and D are comparative examples. In any sample, the relative thickness relationship between the first heat storage layer and the second heat storage layer is the chip fuse according to the present invention. Although different, other configurations are formed in the same manner as the chip fuse of the present invention. In sample A, the first heat storage layer is formed to be approximately 30 μm, and the second heat storage layer is formed to be approximately 30 μm. In the sample B, the first heat storage layer is formed to be approximately 30 μm and the second heat storage layer is formed to be approximately 60 μm. In sample D, the first heat storage layer is formed to be approximately 60 μm, and the second heat storage layer is formed to be approximately 60 μm.
When comparing the sample C, which is an embodiment of the present invention, with the sample D (the first heat storage layer has the same thickness as the sample C), in the range where the rated current ratio is low, as shown in FIG. C has a shorter fusing time than sample D. On the other hand, in the range where the rated current ratio is high, the fusing time of sample C is longer than that of sample D as shown in FIG. From this, it can be seen that the chip fuse of the present invention can prevent the fusing time at a high magnification with respect to the rated current from being shortened and shorten the fusing time at a low magnification with respect to the rated current. .

（ａ）〜（ｄ）はチップヒューズの製造過程を示した平面図である。(A)-(d) is the top view which showed the manufacturing process of the chip fuse. （ｅ）〜（ｈ）は図１に続く製造過程を示した平面図である。(E)-(h) is the top view which showed the manufacturing process following FIG. （ａ）は図２のＡ−Ａ線に沿った断面図、（ｂ）は図２のＢ−Ｂ線に沿った断面図である。(A) is sectional drawing along the AA line of FIG. 2, (b) is sectional drawing along the BB line of FIG. 本発明のチップヒューズと従来例の溶断特性を比較したグラフである。It is the graph which compared the fusing characteristic of the chip fuse of this invention, and a prior art example. 図４における低倍率範囲を拡大して示したグラフである。It is the graph which expanded and showed the low magnification range in FIG. 図４における高倍率範囲を拡大して示したグラフである。It is the graph which expanded and showed the high magnification range in FIG.

符号の説明Explanation of symbols

１０ チップヒューズ
１１ 絶縁基板
１２ 第一の蓄熱層
１３ ヒューズ膜
１３ａ 表電極部
１３ｂ ヒューズ要素部
１４ 溶断部
１５ 第二の蓄熱層 DESCRIPTION OF SYMBOLS 10 Chip fuse 11 Insulation board | substrate 12 1st thermal storage layer 13 Fuse film | membrane 13a Surface electrode part 13b Fuse element part 14 Fusing part 15 2nd thermal storage layer

Claims (3)

熱伝導性の低い膜材料からなる第一の蓄熱層が絶縁基板上に形成され、当該第一の蓄熱層の上に絶縁基板に接触しないようにヒューズ膜が形成され、当該ヒューズ膜は両端に配置される表電極部の間にヒューズ要素部を有するものであり、当該ヒューズ要素部の上に熱伝導性の低い膜材料からなる第二の蓄熱層が形成され、前記第一の蓄熱層が前記第二の蓄熱層よりも厚く形成されたものであるチップヒューズ。   A first heat storage layer made of a film material having low thermal conductivity is formed on an insulating substrate, a fuse film is formed on the first heat storage layer so as not to contact the insulating substrate, and the fuse film is formed at both ends. A fuse element portion is provided between the surface electrode portions to be disposed, a second heat storage layer made of a film material having low thermal conductivity is formed on the fuse element portion, and the first heat storage layer is A chip fuse formed thicker than the second heat storage layer. 熱伝導性の低い膜材料からなる前記第一の蓄熱層及び前記第二の蓄熱層が、感光基を含有するＢステージ状態のシート状材料から形成されたものである請求項１に記載のチップヒューズ。   2. The chip according to claim 1, wherein the first heat storage layer and the second heat storage layer made of a film material having low thermal conductivity are formed from a B-stage sheet material containing a photosensitive group. fuse. 絶縁基板上に第一の蓄熱層が形成され、第一の蓄熱層の上にヒューズ膜が形成され、ヒューズ膜は両端に配置される表電極部の間にヒューズ要素部を有し、ヒューズ要素部の上に第二の蓄熱層が形成されるチップヒューズの製造方法であって、
感光基を含有し、ほぼ均一の厚さに形成されたＢステージ状態のシート状材料を絶縁基板上に所定枚数重畳して第一の蓄熱層を形成する工程と、絶縁基板に接触しないように第一の蓄熱層の上にヒューズ膜を形成するとともに、表電極部の間にヒューズ要素部を形成する工程と、前記第一の蓄熱層に使用した同じＢステージ状態のシート状材料を両表電極部間に所定枚数重畳して第二の蓄熱層を形成する工程とを含み、
前記第一の蓄熱層の形成工程では、前記第二の蓄熱層の形成工程よりも、重畳するＢステージ状態のシート状材料の枚数を多くすることを特徴とするチップヒューズの製造方法。 A first heat storage layer is formed on the insulating substrate, a fuse film is formed on the first heat storage layer, and the fuse film has a fuse element portion between front electrode portions arranged at both ends, and the fuse element A method for manufacturing a chip fuse in which a second heat storage layer is formed on a portion,
A step of forming a first heat storage layer by superposing a predetermined number of B-stage sheet-like materials containing a photosensitive group and formed in a substantially uniform thickness on the insulating substrate, so as not to contact the insulating substrate Forming a fuse film on the first heat storage layer and forming a fuse element portion between the front electrode portions, and the same B-stage sheet-like material used for the first heat storage layer Including a step of forming a second heat storage layer by overlapping a predetermined number of electrodes between the electrode parts,
In the first heat storage layer forming step, the number of sheets of the B-staged sheet material to be superimposed is increased as compared with the second heat storage layer forming step.
JP2008036191A 2008-02-18 2008-02-18 Chip fuse and manufacturing method thereof Active JP4612066B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2008036191A JP4612066B2 (en) 2008-02-18 2008-02-18 Chip fuse and manufacturing method thereof
CN2008800004128A CN101636808B (en) 2008-02-18 2008-02-28 Chip fuse and process for producing the same
KR1020087023427A KR101050243B1 (en) 2008-02-18 2008-02-28 Chip fuse and manufacturing method
PCT/JP2008/053550 WO2009104279A1 (en) 2008-02-18 2008-02-28 Chip fuse and process for producing the same
TW098105128A TWI391974B (en) 2008-02-18 2009-02-18 Chip type fuse and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008036191A JP4612066B2 (en) 2008-02-18 2008-02-18 Chip fuse and manufacturing method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010128078A Division JP5027284B2 (en) 2010-06-03 2010-06-03 Chip fuse and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2009193927A true JP2009193927A (en) 2009-08-27
JP4612066B2 JP4612066B2 (en) 2011-01-12

Family

ID=40985174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008036191A Active JP4612066B2 (en) 2008-02-18 2008-02-18 Chip fuse and manufacturing method thereof

Country Status (5)

Country Link
JP (1) JP4612066B2 (en)
KR (1) KR101050243B1 (en)
CN (1) CN101636808B (en)
TW (1) TWI391974B (en)
WO (1) WO2009104279A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783448A (en) * 2017-02-28 2017-05-31 中山市思福电子厂 A kind of resistance-type coiling fuse and its manufacturing process

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5260592B2 (en) * 2010-04-08 2013-08-14 デクセリアルズ株式会社 Protective element, battery control device, and battery pack
CN101944463B (en) * 2010-08-31 2012-11-28 广东风华高新科技股份有限公司 Film sheet fuse and preparation method thereof
JP5765530B2 (en) * 2011-04-22 2015-08-19 双信電機株式会社 Power fuse
CN104813433B (en) * 2012-09-28 2017-10-24 釜屋电机株式会社 The manufacture method of chip fuse and chip fuse
KR102095225B1 (en) 2019-12-02 2020-03-31 장병철 Chip type fuse using hybrid intergrated circuit technology
KR102095227B1 (en) 2019-12-02 2020-03-31 장병철 Manufacturing method of chip type fuse using thick film printing
CN114765084A (en) * 2021-01-12 2022-07-19 国巨电子（中国）有限公司 Fuse resistor and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050198A (en) * 1996-07-30 1998-02-20 Kyocera Corp Chip fuse element
JPH10162714A (en) * 1996-11-28 1998-06-19 Kyocera Corp Chip fuse element
JP2003234057A (en) * 2003-03-10 2003-08-22 Koa Corp Fuse resistor and its manufacturing method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0935614A (en) * 1995-07-19 1997-02-07 Hitachi Chem Co Ltd Chip fuse and manufacture of it
US6630630B1 (en) * 1999-12-14 2003-10-07 Matsushita Electric Industrial Co., Ltd. Multilayer printed wiring board and its manufacturing method
JP4369010B2 (en) * 2000-04-12 2009-11-18 内橋エステック株式会社 Temperature fuse
JP4112417B2 (en) * 2003-04-14 2008-07-02 釜屋電機株式会社 Chip fuse and manufacturing method thereof
TW200719465A (en) * 2005-11-11 2007-05-16 Inpaq Technology Co Ltd Chip type safety fuse and making method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050198A (en) * 1996-07-30 1998-02-20 Kyocera Corp Chip fuse element
JPH10162714A (en) * 1996-11-28 1998-06-19 Kyocera Corp Chip fuse element
JP2003234057A (en) * 2003-03-10 2003-08-22 Koa Corp Fuse resistor and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783448A (en) * 2017-02-28 2017-05-31 中山市思福电子厂 A kind of resistance-type coiling fuse and its manufacturing process

Also Published As

Publication number Publication date
TW200945398A (en) 2009-11-01
TWI391974B (en) 2013-04-01
KR101050243B1 (en) 2011-07-19
CN101636808A (en) 2010-01-27
CN101636808B (en) 2013-03-20
WO2009104279A1 (en) 2009-08-27
KR20090115652A (en) 2009-11-05
JP4612066B2 (en) 2011-01-12

Similar Documents

Publication Publication Date Title
JP4612066B2 (en) Chip fuse and manufacturing method thereof
CN102045966B (en) The manufacture method of printed substrate
JP4634230B2 (en) Circuit boards, electronic components and electrical junction boxes
JP2009302494A (en) Chip resistor and method for manufacturing the same
US9713267B2 (en) Method for manufacturing printed wiring board with conductive post and printed wiring board with conductive post
TW200402077A (en) Low resistance polymer matrix fuse apparatus and method
KR20060094486A (en) Low resistance polymer matrix fuse apparatus and method
CN103597915A (en) Metal foil patterned-laminate, metal foil laminate, metal foil laminate substrate, solar cell module and manufacturing method for metal foil patterned-laminate
US20090009281A1 (en) Fuse element and manufacturing method thereof
JP2006344477A (en) Chip type fuse
JP4510858B2 (en) Chip fuse and manufacturing method thereof
CN104427755A (en) Flexible circuit board and manufacturing method thereof
JP2009158912A (en) Package substrate and method of manufacturing the same
JP2016066705A (en) Printed wiring board and method for manufacturing the same
TW201306061A (en) Micro-resistive device with soft material layer and manufacture method for the same
JP5027284B2 (en) Chip fuse and manufacturing method thereof
JP2006310277A (en) Chip type fuse
JP2006286224A (en) Chip-type fuse
JP2008306102A (en) Tape carrier for semiconductor device and method of manufacturing same
WO2010081312A1 (en) Laminated surface mounting type thermistor and manufacturing method thereof
JPH0935614A (en) Chip fuse and manufacture of it
JP5117262B2 (en) Wiring board manufacturing method
JP2009272476A (en) Chip resistor and method of manufacturing the same
JP2014060463A (en) Chip resistor and method for manufacturing the same
JP2008270599A (en) Metal plate resistor

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100420

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100603

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100706

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100826

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100921

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101014

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131022

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4612066

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131022

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131022

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250