JP4634230B2 - Circuit boards, electronic components and electrical junction boxes - Google Patents

Circuit boards, electronic components and electrical junction boxes Download PDF

Info

Publication number
JP4634230B2
JP4634230B2 JP2005177709A JP2005177709A JP4634230B2 JP 4634230 B2 JP4634230 B2 JP 4634230B2 JP 2005177709 A JP2005177709 A JP 2005177709A JP 2005177709 A JP2005177709 A JP 2005177709A JP 4634230 B2 JP4634230 B2 JP 4634230B2
Authority
JP
Japan
Prior art keywords
plating layer
solder
circuit board
electronic component
brazing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005177709A
Other languages
Japanese (ja)
Other versions
JP2006351926A (en
Inventor
唯司 富川
功雄 一色
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Wiring Systems Ltd
AutoNetworks Technologies Ltd
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Wiring Systems Ltd
AutoNetworks Technologies Ltd
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Wiring Systems Ltd, AutoNetworks Technologies Ltd, Sumitomo Electric Industries Ltd filed Critical Sumitomo Wiring Systems Ltd
Priority to JP2005177709A priority Critical patent/JP4634230B2/en
Publication of JP2006351926A publication Critical patent/JP2006351926A/en
Application granted granted Critical
Publication of JP4634230B2 publication Critical patent/JP4634230B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1178—Means for venting or for letting gases escape
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

本発明は、回路基板、電子部品及び電気接続箱に関するものである。   The present invention relates to a circuit board, an electronic component, and an electrical junction box.

従来より、自動車のバッテリーから各車載負荷へ電力を分配するための配電回路に、ＦＥＴ等のパワー半導体装置を用いたものが知られている（例えば特許文献１参照）。このようなパワー半導体装置は、例えば半導体チップをダイパッド上に半田等のろう材によって接合し、その半導体チップを封止樹脂により封止した構成になっており、外部に露出されたダイパッドやその他の電極板を回路基板上の導電路に半田付けすることにより基板上に実装される。
特開２００３−１６４０３９公報 2. Description of the Related Art Conventionally, a power semiconductor device such as an FET is used in a power distribution circuit for distributing electric power from an automobile battery to each on-vehicle load (see, for example, Patent Document 1). Such a power semiconductor device has a structure in which, for example, a semiconductor chip is bonded onto a die pad with a brazing material such as solder, and the semiconductor chip is sealed with a sealing resin. The electrode plate is mounted on the substrate by soldering to the conductive path on the circuit substrate.
JP 2003-164039 A

上記のように、半田等のろう材を用いた接合作業の際には、接合しようとする導電路や電極板等とろう材との間に外気が挟み込まれて気泡ができることがある。また、加熱によりろう材や、あるいは導電路や電極板の表面に設けられたメッキ層からガスが発生して気泡となることもある。このようにして、接合後にろう材中に多くの気泡が残ると、ろう材が剥がれやすくなって電気接続の信頼性が損なわれたり、あるいは熱抵抗が大きくなって放熱性が大きく低下するおそれがある。
本発明は上記のような事情に基づいて完成されたものであって、その目的は、半田等のろう材中に残留する気泡を低減することで、放熱性の向上等を図るところにある。 As described above, when joining using a brazing material such as solder, external air may be sandwiched between the conductive path or electrode plate to be joined and the brazing material, thereby generating bubbles. Further, gas may be generated from the brazing material or the plating layer provided on the surface of the conductive path or the electrode plate by heating to form bubbles. In this way, if many bubbles remain in the brazing material after joining, the brazing material may be easily peeled off and the reliability of the electrical connection may be impaired, or the heat resistance may increase and the heat dissipation performance may be greatly reduced. is there.
The present invention has been completed based on the above circumstances, and an object of the present invention is to improve heat dissipation by reducing bubbles remaining in a brazing material such as solder.

上記の目的を達成するための手段として、請求項１の発明に係る回路基板は、電子部品がろう材を用いて接合される導電路を備えた回路基板であって、前記導電路は、銅箔からなる基材の表面にメッキ層を設けてなり、前記導電路の表面には、接合時に気体を逃がすための逃がし溝が、前記メッキ層の一部を除去することで形成されているところに特徴を有する。 As a means for achieving the above object, a circuit board according to the invention of claim 1 is a circuit board provided with a conductive path to which an electronic component is bonded using a brazing material, and the conductive path is made of copper. A plating layer is provided on the surface of a base material made of foil, and an escape groove for releasing gas at the time of joining is formed on the surface of the conductive path by removing a part of the plating layer. It has the characteristics.

請求項２の発明は、請求項１に記載のものにおいて、前記逃がし溝の底部は、周辺部よりも前記ろう材の濡れ性が低くされているところに特徴を有する。   The invention of claim 2 is characterized in that, in the invention of claim 1, the bottom part of the escape groove has a lower wettability of the brazing material than the peripheral part.

請求項３の発明は、請求項１または２に記載のものにおいて、前記逃がし溝は、前記メッキ層が線状に除去されてなるところに特徴を有する。 A third aspect of the invention is characterized in that, in the first or second aspect of the invention, the relief groove is formed by removing the plating layer in a linear shape.

請求項４の発明は、請求項１または２に記載のものにおいて、前記逃がし溝は、前記メッキ層が格子状に除去されてなるところに特徴を有する。 According to a fourth aspect of the present invention, the relief groove according to the first or second aspect is characterized in that the plating layer is removed in a lattice shape.

請求項５の発明に係る電子部品は、外部の導電路にろう材を用いて接合される電極板を有した電子部品であって、前記電極板の表面には、接合時に気体を逃がすための逃がし溝が形成されているところに特徴を有する。 An electronic component according to a fifth aspect of the present invention is an electronic component having an electrode plate that is bonded to an external conductive path using a brazing material. The surface of the electrode plate is for releasing gas during bonding. It is characterized in that a relief groove is formed.

請求項６の発明は、請求項５に記載のものにおいて、前記逃がし溝の底部は、周辺部よりも前記ろう材の濡れ性が低くされているところに特徴を有する。 A sixth aspect of the present invention is characterized in that, in the fifth aspect of the present invention, the bottom portion of the escape groove has a lower wettability of the brazing material than the peripheral portion.

請求項７の発明は、請求項５または６に記載のものにおいて、前記逃がし溝は、前記メッキ層が線状に除去されてなるところに特徴を有する。 A seventh aspect of the invention is characterized in that, in the fifth or sixth aspect , the escape groove is formed by removing the plating layer in a linear shape.

請求項８の発明は、請求項５または６に記載のものにおいて、前記逃がし溝は、前記メッキ層が格子状に除去されてなるところに特徴を有する。 The invention of claim 8 is characterized in that, in the invention of claim 5 or 6 , the relief groove is formed by removing the plating layer in a lattice shape.

請求項９の発明に係る回路基板は、請求項５から請求項８のいずれか一項に記載の電子部品を実装したところに特徴を有する。 A circuit board according to a ninth aspect of the invention is characterized in that the electronic component according to any one of the fifth to eighth aspects is mounted.

請求項１０の発明に係る電気接続箱は、請求項１から請求項４及び請求項９のいずれか一項に記載の回路基板を備えたところに特徴を有する。 An electrical junction box according to the invention of claim 10 is characterized in that the circuit board according to any one of claims 1 to 4 and claim 9 is provided.

＜請求項１の発明＞
導電路の表面に逃がし溝が形成されているため、ろう材による接合時に気体が逃がし溝により逃がされる。これにより、ろう材中に残留する気泡を低減することができ、放熱性を向上させることができる。
また、逃がし溝は、メッキ層の一部を除去することで形成されるため、簡易に形成することができる。 <Invention of Claim 1>
Since the escape groove is formed on the surface of the conductive path, gas is escaped by the escape groove when joining with the brazing material. Thereby, bubbles remaining in the brazing material can be reduced, and heat dissipation can be improved.
Further, the escape groove can be easily formed because it is formed by removing a part of the plating layer.

＜請求項２及び請求項６の発明＞
逃がし溝の底部が周辺部に比べてろう材の濡れ性が低くなっているため、接合時に逃がし溝がろう材で埋められにくくなる。従って、逃がし溝の通気性を確保することができる。 <Invention of Claims 2 and 6 >
Since the wettability of the brazing material is lower at the bottom of the escape groove than at the periphery, the escape groove is less likely to be filled with the brazing material at the time of joining. Therefore, the air permeability of the escape groove can be ensured.

＜請求項３及び請求項７の発明＞
逃がし溝は、メッキ層を線状に除去することで形成されている。このため、逃がし溝を例えばレーザ等によって簡易に形成することができる。 <Invention of Claim 3 and Claim 7 >
The escape groove is formed by removing the plating layer in a linear shape. For this reason, the escape groove can be easily formed by, for example, a laser.

＜請求項４及び請求項８の発明＞
逃がし溝は、メッキ層を格子状に除去することで形成されている。このため、逃がし溝を例えばレーザ等によって簡易に形成することができる。また、ろう材の流動を抑えることができる。 <Invention of Claims 4 and 8 >
The escape groove is formed by removing the plating layer in a lattice shape. For this reason, the escape groove can be easily formed by, for example, a laser. Moreover, the flow of the brazing material can be suppressed.

＜請求項５、請求項９及び請求項１０の発明＞
導電板の表面に逃がし溝が形成されているため、ろう材による接合時に気体が逃がし溝により逃がされる。これにより、ろう材中に残留する気泡を低減することができ、放熱性を向上させることができる。 <Invention of Claims 5 , 9, and 10 >
Since the escape groove is formed on the surface of the conductive plate, gas is escaped by the escape groove when joining with the brazing material. Thereby, bubbles remaining in the brazing material can be reduced, and heat dissipation can be improved.

＜実施形態１＞
以下、本発明の実施形態１を図１ないし図４によって説明する。
本実施形態のパワー半導体装置１（本発明の電子部品に相当）は、自動車のバッテリーから各車載負荷へ電力を分配するために用いられる電気接続箱（図示せず）の一構成部品として用いられる。電気接続箱は、配電回路を構成する回路構成体２（本発明の回路基板に相当）をケース（図示せず）内に収容してなり、図１に示すように、この回路構成体２上にパワー半導体装置１が実装されている。 <Embodiment 1>
Embodiment 1 of the present invention will be described below with reference to FIGS.
The power semiconductor device 1 (corresponding to the electronic component of the present invention) of the present embodiment is used as a component of an electrical junction box (not shown) used for distributing electric power from a vehicle battery to each vehicle load. . The electrical junction box is configured by housing a circuit structure 2 (corresponding to the circuit board of the present invention) constituting the power distribution circuit in a case (not shown). As shown in FIG. A power semiconductor device 1 is mounted.

回路構成体２は、いわゆる両面プリント基板であって、絶縁性のベース基板３の表裏両面に、銅箔からなる導電路４及び絶縁皮膜５（ソルダーレジスト）のパターンを印刷することで形成されている。導電路４の一部は、絶縁皮膜５から露出されており、その露出部分において、図２にも示すように、銅箔４Ａの表面に半田濡れ性に優れたＮｉメッキ層４Ｂが形成されることで、パワー半導体装置１等の電子部品が接続されるランド部６，７が形成されている。   The circuit structure 2 is a so-called double-sided printed board, and is formed by printing a pattern of a conductive path 4 and an insulating film 5 (solder resist) made of copper foil on both front and back sides of an insulating base board 3. Yes. A part of the conductive path 4 is exposed from the insulating film 5, and an Ni plating layer 4B having excellent solder wettability is formed on the surface of the copper foil 4A at the exposed portion as shown in FIG. Thus, land portions 6 and 7 to which electronic components such as the power semiconductor device 1 are connected are formed.

パワー半導体装置１は、図１に示すように、平板状のダイパッド部１０（本発明の電極板に相当）を備えており、その上面にＭＯＳ−ＦＥＴチップ１１が半田１２により接合され、さらにそのＭＯＳ−ＦＥＴチップ１１が封止樹脂１４により封止されている。ダイパッド部１０は、図２にも示すように、銅合金からなる基材１０Ａの表面に半田濡れ性が良好なＮｉ等のメッキ層１０Ｂが設けられている。また、ダイパッド部１０は、底面が封止樹脂１４の外側に露出しており、その底面が半田１５によりランド部７に接合されている。また、封止樹脂１４の一側面からは、複数本のリード部１６が延出されている。各リード部１６は、ＭＯＳ−ＦＥＴチップ９の電極にボンディングワイヤ（図示せず）を介して接続されており、外側に延出した端部が半田１７によりランド部６に接合されている。   As shown in FIG. 1, the power semiconductor device 1 includes a flat die pad portion 10 (corresponding to the electrode plate of the present invention), and a MOS-FET chip 11 is joined to the upper surface thereof by solder 12. The MOS-FET chip 11 is sealed with a sealing resin 14. As shown in FIG. 2, the die pad portion 10 is provided with a plating layer 10B made of Ni or the like having good solder wettability on the surface of a base material 10A made of a copper alloy. Further, the bottom surface of the die pad portion 10 is exposed outside the sealing resin 14, and the bottom surface is joined to the land portion 7 by the solder 15. Further, a plurality of lead portions 16 are extended from one side surface of the sealing resin 14. Each lead portion 16 is connected to an electrode of the MOS-FET chip 9 via a bonding wire (not shown), and an end portion extending outward is joined to the land portion 6 by a solder 17.

ダイパッド部１０の上下面、即ち半田１２，１５による接合がなされる面には、図２及び図３に示すように、格子状の逃がし溝２０が形成されている。この逃がし溝２０は、例えばダイパッド部１０の表面にレーザ光線を照射して、メッキ層１０Ｂの一部を除去することで形成される。このようにしてメッキ層１０Ｂの一部が除去されると、除去された部分から露出した銅合金よりなる基材１０Ａの表面が酸化して酸化皮膜（図示せず）が形成される。このため、逃がし溝２０の底部は、メッキ層１０Ｂの表面に比べて半田濡れ性が低くなっている。   As shown in FIGS. 2 and 3, lattice-shaped escape grooves 20 are formed on the upper and lower surfaces of the die pad portion 10, that is, the surfaces to be joined by the solders 12 and 15. The escape groove 20 is formed, for example, by irradiating the surface of the die pad portion 10 with a laser beam and removing a part of the plating layer 10B. When a part of the plating layer 10B is removed in this way, the surface of the base material 10A made of the copper alloy exposed from the removed part is oxidized to form an oxide film (not shown). For this reason, the solder wettability is lower at the bottom of the escape groove 20 than at the surface of the plating layer 10B.

一方、回路構成体２におけるランド部７の表面にも、図２及び図４に示すように、格子状の逃がし溝２１が形成されている。この逃がし溝２１も、ランド部７の表面へのレーザ光線の照射等により、メッキ層４Ｂの一部を除去することで形成される。逃がし溝２１の底部は、銅箔４Ａの表面に形成された酸化皮膜により、メッキ層４Ｂの表面に比べて半田濡れ性が低くなっている。   On the other hand, a lattice-shaped escape groove 21 is also formed on the surface of the land portion 7 in the circuit structure 2 as shown in FIGS. The escape groove 21 is also formed by removing a part of the plating layer 4B by irradiating the surface of the land portion 7 with a laser beam or the like. The bottom of the escape groove 21 has a lower solder wettability than the surface of the plating layer 4B due to the oxide film formed on the surface of the copper foil 4A.

パワー半導体装置１を回路構成体２上に実装する場合には、まず回路構成体２の各ランド部６，７にスクリーン印刷等によりペースト状の半田１５，１７を印刷する。そして、その半田１５，１７の上に、パワー半導体装置１のリード部１６及びダイパッド部１０を載置し、リフロー炉（図示せず）で半田溶融温度まで加熱、冷却することにより、リード部１６及びダイパッド部１０と、各ランド部６，７とを半田付けする。   When the power semiconductor device 1 is mounted on the circuit structure 2, first, paste-like solders 15 and 17 are printed on the land portions 6 and 7 of the circuit structure 2 by screen printing or the like. Then, the lead part 16 and the die pad part 10 of the power semiconductor device 1 are placed on the solders 15 and 17, and the lead part 16 is heated and cooled to the solder melting temperature in a reflow furnace (not shown). And the die pad part 10 and each land part 6 and 7 are soldered.

上記接合工程において、リフロー炉にて半田１５が溶融すると、その半田１５が濡れ性の良いランド部７及びダイパッド部１０のメッキ層４Ｂ，１０Ｂの表面を伝って濡れ拡がる一方で、濡れ性の低い逃がし溝２０，２１の底部には付着しない。このため、ダイパッド部１０若しくは導電路４と半田１５との間に挟まれた外気や、半田１５やメッキ層４Ｂ，１０Ｂから発生したガスが逃がし溝２０，２１を通じて外部に逃がされる。これにより、冷却後に半田１５中に残留する気泡が低減される。また、同じく上記の接合工程においては、逃がし溝２０，２１が格子状に形成されることで半田濡れ性が良好なメッキ層４Ｂ，１０Ｂがブロック状に分断されているため、半田１５がそのブロックよりも外側に流動しにくくなる。このため、半田溶融時にパワー半導体装置１が半田の流動に伴って移動することが防止され、部品の位置決めの精度を高めることができる。   In the above bonding step, when the solder 15 is melted in the reflow furnace, the solder 15 spreads on the surface of the plating layers 4B and 10B of the land portion 7 and the die pad portion 10 with good wettability, but has low wettability. It does not adhere to the bottoms of the escape grooves 20 and 21. For this reason, the air generated between the die pad 10 or the conductive path 4 and the solder 15 and the gas generated from the solder 15 and the plating layers 4B and 10B are released to the outside through the escape grooves 20 and 21. Thereby, bubbles remaining in the solder 15 after cooling are reduced. Similarly, in the above joining step, the relief grooves 20 and 21 are formed in a lattice shape, so that the plating layers 4B and 10B having good solder wettability are divided into blocks, so that the solder 15 is blocked. It becomes difficult to flow outward. For this reason, it is possible to prevent the power semiconductor device 1 from moving with the flow of the solder when the solder is melted, and to improve the positioning accuracy of the components.

なお、パワー半導体装置１の製造の際には、ダイパッド部１０の上面にＭＯＳ−ＦＥＴチップ９が半田１２により接合される。この半田付け作業は加熱処理により行われるが、この工程においてもダイパッド部１０と半田１２との間に挟まれた外気や、半田１２やメッキ層１０Ｂから発生したガスが、ダイパッド部１０の上面に設けられた逃がし溝２０により外部に逃がされる。また、逃がし溝２０が格子状に形成されることで半田濡れ性が良好なメッキ層１０Ｂがブロック状に分断されているため、半田１２が流動しにくくなる。このため、半田溶融時にＭＯＳ−ＦＥＴチップ９が半田の流動に伴って移動することが防止され、位置決め精度を高めることができる。   In manufacturing the power semiconductor device 1, the MOS-FET chip 9 is joined to the upper surface of the die pad portion 10 by the solder 12. This soldering operation is performed by heat treatment. In this process as well, the outside air sandwiched between the die pad portion 10 and the solder 12 and the gas generated from the solder 12 and the plating layer 10B are applied to the upper surface of the die pad portion 10. It is escaped to the outside by the provided relief groove 20. Further, since the relief grooves 20 are formed in a lattice shape, the plating layer 10B having good solder wettability is divided into blocks, so that the solder 12 is difficult to flow. For this reason, it is possible to prevent the MOS-FET chip 9 from moving along with the flow of the solder when the solder is melted, and to improve the positioning accuracy.

以上のように本実施形態によれば、ランド部７及びダイパッド部１０の表面に逃がし溝２０，２１が形成されているため、半田による接合時に気体が逃がし溝２１により逃がされる。これにより、半田中に残留する気泡を低減することができ、放熱性を向上させることができる。   As described above, according to the present embodiment, since the escape grooves 20 and 21 are formed on the surfaces of the land portion 7 and the die pad portion 10, gas is released by the escape groove 21 during joining by soldering. Thereby, bubbles remaining in the solder can be reduced, and heat dissipation can be improved.

逃がし溝２０，２１の底部が周辺部（メッキ層４Ｂ，１０Ｂの表面）に比べて半田濡れ性が低くなっているため、接合時に逃がし溝２０，２１が半田で埋められにくくなる。従って、逃がし溝２０，２１の通気性を確保することができる。   Since the bottoms of the escape grooves 20 and 21 are lower in solder wettability than the peripheral parts (the surfaces of the plating layers 4B and 10B), the escape grooves 20 and 21 are difficult to be filled with solder at the time of joining. Therefore, the air permeability of the escape grooves 20 and 21 can be ensured.

逃がし溝２０，２１は、メッキ層４Ｂ，１０Ｂの一部を除去することで形成されるため、簡易に形成することができる。   Since the escape grooves 20 and 21 are formed by removing a part of the plating layers 4B and 10B, they can be easily formed.

また、逃がし溝２０，２１は、メッキ層４Ｂ，１０Ｂを線状または格子状に除去することで形成されている。このため、逃がし溝２０，２１を例えばレーザ等によって簡易に形成することができる。また、逃がし溝２０，２１が格子状に形成されているため、半田の流動を抑えることができる。   Further, the escape grooves 20 and 21 are formed by removing the plating layers 4B and 10B in a linear shape or a lattice shape. For this reason, the escape grooves 20 and 21 can be easily formed by a laser or the like, for example. Further, since the escape grooves 20 and 21 are formed in a lattice shape, the flow of solder can be suppressed.

＜他の実施形態＞
本発明は上記記述及び図面によって説明した実施形態に限定されるものではなく、例えば次のような実施形態も本発明の技術的範囲に含まれ、さらに、下記以外にも要旨を逸脱しない範囲内で種々変更して実施することができる。
（１）上記実施形態では、ろう材として半田を用いたものを示したが、半田以外のろう材、例えば銀ろう等の硬ろうを用いたものも本発明に含まれる。
（２）上記実施形態では、逃がし溝を格子状に形成したものを示したが、逃がし溝の形状は適宜変更できる。例えば図５に示したものでは、線状の８本の逃がし溝２１Ａがランド部７の中心から放射状に延びて形成されている。また、図６に示したものでは、ランド部７のうち中央を除いた外周部に８本の線状の逃がし溝２１Ｂが放射状に延びて形成されている。
（３）上記実施形態では、逃がし溝をダイパッド部とダイパッド部が接合されるランド部に設けたものを示したが、本発明によれば、電子部品が有するダイパッド部以外の電極板（リード部等）や、その電極板と接合される回路基板の導電路に逃がし溝を設けても良い。
（４）上記実施形態に例示した製造工程はあくまでも一例であって、適宜に変更可能である。
（５）メッキ層は、異なる成分を含む層が複数積層されたものであっても良い。この場合、逃がし溝を形成するために、メッキ層を形成する複数の層の全てを削っても良く、表面側の一部の層のみを削っても良い。
（６）逃がし溝は、導電路、電極板のメッキ層を削って形成しても良い。 <Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention, and further, within the scope not departing from the gist of the invention other than the following. Various modifications can be made.
(1) In the above embodiment, the soldering material is used as the brazing material. However, a soldering material other than solder, for example, a soldering material such as silver solder is also included in the present invention.
(2) In the above embodiment, the relief grooves are formed in a lattice shape, but the shape of the relief grooves can be changed as appropriate. For example, in the case shown in FIG. 5, eight linear relief grooves 21 </ b> A are formed extending radially from the center of the land portion 7. Moreover, in the thing shown in FIG. 6, the eight linear escape grooves 21B are radially extended and formed in the outer peripheral part except the center among the land parts 7. In FIG.
(3) In the above embodiment, the relief groove is provided in the land portion where the die pad portion and the die pad portion are joined. However, according to the present invention, the electrode plate (lead portion) other than the die pad portion included in the electronic component is shown. Etc.) or a relief groove may be provided in the conductive path of the circuit board to be joined to the electrode plate.
(4) The manufacturing process illustrated in the above embodiment is merely an example, and can be changed as appropriate.
(5) The plating layer may be a laminate of a plurality of layers containing different components. In this case, in order to form the relief groove, all of the plurality of layers forming the plating layer may be removed, or only a part of the surface side layer may be removed.
(6) The escape groove may be formed by cutting the conductive path and the plating layer of the electrode plate .

本発明の実施形態１に係るパワー半導体装置と回路構成体の断面図Sectional drawing of the power semiconductor device and circuit structure which concern on Embodiment 1 of this invention ダイパッド部と導電路との半田接合部分を示す部分拡大断面図Partial expanded sectional view which shows the solder joint part of a die pad part and a conductive path ダイパッド部の平面図Plan view of die pad ランド部の平面図Land plan view 他の実施形態に係る逃がし溝を示す平面図The top view which shows the escape groove which concerns on other embodiment 別の他の実施形態に係る逃がし溝を示す平面図The top view which shows the escape groove which concerns on another other embodiment

符号の説明Explanation of symbols

１…パワー半導体装置
２…回路構成体（回路基板）
４…導電路
７Ａ…銅箔（基材）
７Ｂ…メッキ層
１０…ダイパッド部（電極板）
１０Ａ…基材
１０Ｂ…メッキ層
１２，１５…半田（ろう材）
２０，２１，２１Ａ，２１Ｂ…逃がし溝 DESCRIPTION OF SYMBOLS 1 ... Power semiconductor device 2 ... Circuit structure (circuit board)
4 ... Conductive path 7A ... Copper foil (base material)
7B ... Plating layer 10 ... Die pad part (electrode plate)
10A ... Base material 10B ... Plating layers 12, 15 ... Solder (brazing material)
20, 21, 21A, 21B ... Relief groove

Claims (10)

電子部品がろう材を用いて接合される導電路を備えた回路基板であって、
前記導電路は、銅箔からなる基材の表面にメッキ層を設けてなり、
前記導電路の表面には、接合時に気体を逃がすための逃がし溝が、前記メッキ層の一部を除去することで形成されていることを特徴とする回路基板。 A circuit board having a conductive path to which an electronic component is bonded using a brazing material,
The conductive path is provided with a plating layer on the surface of a base material made of copper foil,
A circuit board, wherein a relief groove for allowing gas to escape at the time of bonding is formed on a surface of the conductive path by removing a part of the plating layer. 前記逃がし溝の底部は、周辺部よりも前記ろう材の濡れ性が低くされていることを特徴とする請求項１に記載の回路基板。 2. The circuit board according to claim 1, wherein a wettability of the brazing material is lower in a bottom portion of the escape groove than in a peripheral portion. 前記逃がし溝は、前記メッキ層が線状に除去されてなることを特徴とする請求項１または請求項２に記載の回路基板。 The circuit board according to claim 1, wherein the relief groove is formed by removing the plating layer in a linear shape. 前記逃がし溝は、前記メッキ層が格子状に除去されてなることを特徴とする請求項１または請求項２に記載の回路基板。 The circuit board according to claim 1, wherein the relief groove is formed by removing the plating layer in a lattice shape. 外部の導電路にろう材を用いて接合される電極板を有した電子部品であって、
前記電極板は、銅合金からなる基材の表面にメッキ層を設けて構成され、
前記電極板の表面には、接合時に気体を逃がすための逃がし溝が、前記メッキ層の一部を除去することで形成されていることを特徴とする電子部品。 An electronic component having an electrode plate joined to the external conductive path using a brazing material,
The electrode plate is configured by providing a plating layer on the surface of a base material made of a copper alloy,
An electronic component, wherein a relief groove for allowing gas to escape at the time of joining is formed on the surface of the electrode plate by removing a part of the plating layer. 前記逃がし溝の底部は、周辺部よりも前記ろう材の濡れ性が低くされていることを特徴とする請求項５に記載の電子部品。 The electronic component according to claim 5, wherein a wettability of the brazing material is lower in a bottom portion of the escape groove than in a peripheral portion. 前記逃がし溝は、前記メッキ層が線状に除去されてなることを特徴とする請求項５または請求項６に記載の電子部品。 The electronic component according to claim 5, wherein the relief groove is formed by removing the plating layer in a linear shape. 前記逃がし溝は、前記メッキ層が格子状に除去されてなることを特徴とする請求項５または請求項６に記載の電子部品。 The electronic component according to claim 5, wherein the relief groove is formed by removing the plating layer in a lattice shape. 請求項５から請求項８のいずれか一項に記載の電子部品を実装した回路基板。 The circuit board which mounted the electronic component as described in any one of Claims 5-8. 請求項１から請求項４及び請求項９のいずれか一項に記載の回路基板を備えた電気接続箱。 An electrical junction box comprising the circuit board according to any one of claims 1 to 4 and claim 9.
JP2005177709A 2005-06-17 2005-06-17 Circuit boards, electronic components and electrical junction boxes Expired - Fee Related JP4634230B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005177709A JP4634230B2 (en) 2005-06-17 2005-06-17 Circuit boards, electronic components and electrical junction boxes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005177709A JP4634230B2 (en) 2005-06-17 2005-06-17 Circuit boards, electronic components and electrical junction boxes

Publications (2)

Publication Number Publication Date
JP2006351926A JP2006351926A (en) 2006-12-28
JP4634230B2 true JP4634230B2 (en) 2011-02-16

Family

ID=37647436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005177709A Expired - Fee Related JP4634230B2 (en) 2005-06-17 2005-06-17 Circuit boards, electronic components and electrical junction boxes

Country Status (1)

Country Link
JP (1) JP4634230B2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101702952B (en) * 2007-12-28 2011-09-14 欧南芭株式会社 Terminal board circuit
JP4929382B2 (en) * 2010-07-13 2012-05-09 株式会社東芝 Electronic component structure and electronic device
ITMI20111776A1 (en) * 2011-09-30 2013-03-31 St Microelectronics Srl ELECTRONIC SYSTEM FOR REFLOW SOLDERING
US8587019B2 (en) * 2011-10-11 2013-11-19 Ledengin, Inc. Grooved plate for improved solder bonding
JP2014060211A (en) * 2012-09-14 2014-04-03 Omron Corp Substrate structure, semiconductor chip mounting method and solid state relay
JP6068645B2 (en) * 2013-07-30 2017-01-25 京セラ株式会社 Wiring board and electronic device
JP6206021B2 (en) * 2013-09-12 2017-10-04 三菱電機株式会社 Power semiconductor device manufacturing method and power semiconductor device
JP2016127207A (en) * 2015-01-07 2016-07-11 三菱電機株式会社 Mounting board and manufacturing method for the same, and printed wiring plate and electronic component
CN108028232B (en) * 2015-10-27 2021-09-24 京瓷株式会社 Wiring substrate, electronic device, and electronic module
JP6569610B2 (en) * 2016-07-06 2019-09-04 株式会社デンソー Electronic equipment
JP6757006B2 (en) * 2016-10-21 2020-09-16 国立研究開発法人産業技術総合研究所 Semiconductor devices and their manufacturing methods
JP7168280B2 (en) * 2018-06-26 2022-11-09 住友電工デバイス・イノベーション株式会社 Semiconductor device and semiconductor chip mounting method
CN109273423A (en) * 2018-08-22 2019-01-25 宁波天炬光电科技有限公司 Chip structure, wafer-level package enhancing structure and method
DE102018125300A1 (en) * 2018-10-12 2020-04-16 Osram Opto Semiconductors Gmbh Electronic component and method for applying at least one solder pad to an electronic component
JP2020136431A (en) * 2019-02-18 2020-08-31 株式会社東芝 Semiconductor device manufacturing method and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220281A (en) * 1983-05-28 1984-12-11 Nippon Light Metal Co Ltd Brazing and joining method of metallic body
JPH1131876A (en) * 1997-07-10 1999-02-02 Murata Mfg Co Ltd Circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220281A (en) * 1983-05-28 1984-12-11 Nippon Light Metal Co Ltd Brazing and joining method of metallic body
JPH1131876A (en) * 1997-07-10 1999-02-02 Murata Mfg Co Ltd Circuit board

Also Published As

Publication number Publication date
JP2006351926A (en) 2006-12-28

Similar Documents

Publication Publication Date Title
JP4634230B2 (en) Circuit boards, electronic components and electrical junction boxes
JP5100081B2 (en) Electronic component-mounted multilayer wiring board and manufacturing method thereof
JP6021504B2 (en) Printed wiring board, printed circuit board, and printed circuit board manufacturing method
JP4438489B2 (en) Semiconductor device
JP2005095977A (en) Circuit device
JP2014060211A (en) Substrate structure, semiconductor chip mounting method and solid state relay
JP2017212316A (en) Metal-ceramic bonding substrate and manufacturing method thereof
JP2008187101A (en) Semiconductor device and mounting structure of semiconductor device
JP2006060141A (en) Printed board and mounting method for surface mounted semiconductor package using same
JP2006318986A (en) Flexible printed circuit board and its manufacturing method
JP2006351927A (en) Semiconductor device, circuit board, and electric connection box
JP6587795B2 (en) Circuit module
JP6477105B2 (en) Semiconductor device
JP5539453B2 (en) Electronic component-mounted multilayer wiring board and manufacturing method thereof
KR101735439B1 (en) Manufacturing method for radiant heat circuit board
JP5044259B2 (en) Circuit structure
JP6027626B2 (en) Manufacturing method of component-embedded substrate
JP2013171963A (en) Printed circuit board device, and electronic apparatus
JP6633151B2 (en) Circuit module
JP2018046225A (en) Board device
CN110931447A (en) Module and printed circuit board
US8598597B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP2009105327A (en) Semiconductor device with heat sink and its method for manufacturing
JP2008282904A (en) Molded package, and manufacturing method thereof
JP2007073648A (en) Wiring board

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20070427

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080321

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20090909

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090909

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100519

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100525

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100716

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100914

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101019

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101111

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101118

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131126

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees