JP6757006B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to a technique for enhancing the crack resistance of the soldered portion against repeated temperature changes in a structure in which a semiconductor chip is solder-bonded to a metal plate.

A vertical semiconductor chip, which is often used mainly for electric power, has a metal film that also serves as one main electrode on the entire back surface, and is used by joining this to a metal plate that serves as external wiring via a solder layer. In addition, this structure is connected to the appropriate radiator. Such a mounting structure experiences repeated temperature changes due to heat generation of the semiconductor chip itself due to driving, changes in ambient temperature, and the like. Then, due to the difference in the coefficient of thermal expansion between the semiconductor chip and the metal plate, repeated shear stress is applied to the solder layer that joins them. Eventually, cracks occur on the surface of the solder layer near the corners of the chip where stress is most concentrated, and as the temperature changes repeatedly, they propagate inward, increasing the electrical resistance and thermal resistance of the semiconductor chip. Therefore, in practice, the life of this joint structure is defined as the time when the electrical resistance and thermal resistance rise to appropriate values, and the use is terminated. The service life varies depending on the repeated temperature difference and the number of repetitions.

When joining a semiconductor chip to a metal land portion on an insulating substrate via a solder material, for example, as disclosed in Patent Document 1, with the intention of suppressing the occurrence or growth of such cracks. A fixed structure of a semiconductor chip is known in which a connection strengthening space is formed in a solder connection portion by cutting out a peripheral portion thereof in advance on the bottom surface of the semiconductor chip. Further, for example, in Patent Document 2, a connecting material having a plurality of Al-based phases is interposed inside a Zn—Al-based alloy layer and solder-bonded between the semiconductor chip and a metal support member. , A semiconductor device having a stress buffering function due to thermal shock is known.

Japanese Unexamined Patent Publication No. 6-177178 Japanese Unexamined Patent Publication No. 2012-629

However, in the configuration disclosed in Patent Document 1, the back surface of the semiconductor chip needs to be cut as a pretreatment for forming a solder joint. In order to perform such processing, advanced technological development is required separately, and further, the manufacturing time and manufacturing cost are increased due to the addition of processes. On the other hand, in the configuration disclosed in Patent Document 2, since plate solder in which an Al-based phase metal piece is additionally enclosed between the solder base materials is used, a high level of technology is required for the production of the connecting material itself. It also costs money.

The present invention has been devised to solve such a problem, and provides a mounting structure having high crack resistance of the solder joint layer against repeated temperature changes without relying on cutting processing on a semiconductor chip or a special solder material. It is a thing.

That is, as a solution according to the present invention, for example, a semiconductor device in which a metal electrode formed on one main surface (here, the back surface) of a semiconductor chip and a metal plate are joined by a solder layer, the solder. The layer has a plurality of gaps extending in the direction from the metal electrode to the metal plate, and both side surfaces of the solder layer facing each other through the gaps are covered with an oxide film. It should be noted that there are a plurality of the gaps, and at least partially, they may run in parallel with each other to form a striped shape, may intersect vertically and horizontally to form a mesh shape, or at least the outer periphery of the semiconductor chip. In the vicinity, it may form a substantially corridor.

According to such a configuration, even if the solder layer is distorted due to the repeated thermal change and the difference in the coefficient of thermal expansion between the semiconductor chip and the metal plate, the solder layers separated by the gaps are compared. Since it can be deformed flexibly, cracks are unlikely to occur, and even if cracks occur in a part of the solder blocks, the presence of the gaps prevents the cracks from reaching the adjacent solder layers, and the electricity of the semiconductor chip Resistance and thermal resistance are kept with minimal changes. It should be noted that this corresponds to claims 1, 3, 4, and 5.

Further, the distance between the plurality of gaps is narrower in the vicinity of the outer circumference than in the vicinity of the center of the semiconductor chip. In this way, the aspect ratio of the solder block sandwiched between the gaps becomes high in the vicinity of the outer circumference. On the other hand, the displacement generated in the solder layer due to the difference in the coefficient of thermal expansion between the semiconductor chip and the metal plate is larger in the vicinity of the outer periphery than in the vicinity of the center of the semiconductor chip. However, if the aspect ratio of the solder block is high in that region, the strain applied to the solder block itself is suppressed and cracks are less likely to occur. This corresponds to claim 6.

Further, the solder layer may be made of a Zn—Al alloy. This alloy is known as high temperature solder, and since the surface forms a strong oxide film only when it comes into contact with air, the structure of the present invention can be realized relatively easily. It should be noted that this corresponds to claim 2.

Further, in the semiconductor device according to the present invention, a temporary joining step of arranging and temporarily joining block-shaped solders formed in advance on the surface of the metal plate, an oxidation step of oxidizing the exposed solder surface, and the semiconductor on the temporary joining step. This can be realized by a manufacturing method including a main joining step in which the metal electrodes of the chip are brought into contact with each other, heated to a temperature equal to or higher than the melting point of the block-shaped solder, and then cooled to join the whole. This corresponds to claim 7.

Alternatively, the plate solder may be placed and temporarily joined, and then a molding step of processing the plate solder to form a gap may be performed, and then the oxidation step and the main joining may be performed. This corresponds to claim 8.

In the case of these manufacturing methods, if the region on the surface of the metal electrode of the semiconductor chip on which the gap is to be formed is subjected to a reforming treatment step of repelling the molten solder, the gap is further separated. Is ensured, and the effect of stress relaxation is increased. This corresponds to claim 9.

Further, as another manufacturing method, there is a modification treatment step of making the region on the surface of the metal plate where the gaps should be formed into a property of repelling molten solder, and a plate solder is placed on the surface of the metal plate. A temporary joining step of temporarily joining the solder, an island forming step of melting the plate solder to form solder islands in a region of the metal plate not subjected to the modification treatment, and cooling and solidifying the solder. In the oxidation step of oxidizing the surface of the island of solder, and in a state where the metal electrode of the semiconductor chip is in contact with the island of solder, the molten solder is heated to the melting point of the island of solder or higher to form the metal electrode. It may be a manufacturing method including a main joining step in which the whole is joined after being wetted and then cooled. In this way, the gap can be easily realized in a self-aligned manner. This corresponds to claim 10.

Further, in the entire manufacturing method, when the region on the surface of the metal electrode formed on the semiconductor chip where the gap is to be formed is subjected to a modification treatment of repelling molten solder, the gap is further formed. The separation is ensured and the effect of stress relaxation is increased. This corresponds to claim 11.

The modification treatment for repelling the molten solder and the metal electrode modification treatment include a treatment for locally oxidizing the metal surface, a treatment for removing the surface metal having good wettability to the molten solder, and conversely, the molten solder. It is a process to locally deposit an oxide film that repels solder. This corresponds to claims 12, 13 and 14.

It is sectional drawing explaining the junction structure of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing explaining the modification of the bonding state in FIG. It is sectional drawing explaining the operation of this invention. It is a perspective view explaining the specific shape of the solder layer applied in relation to FIG. It is sectional drawing explaining the modification of the semiconductor device by 1st Embodiment of this invention. It is a perspective view explaining the modification of the concrete shape of the solder layer applied in relation to FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining another manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining still another manufacturing method of the semiconductor device shown in FIG. FIG. 5 is a top view of a plate solder for explaining a processing example in relation to FIG. It is sectional drawing explaining still another manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method shown in FIG.

Hereinafter, the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 6.

FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device 100 according to the first embodiment of the present invention. In the figure, reference numeral 130 denotes a semiconductor chip, and a back metal film 132 is formed on the back surface thereof. Reference numeral 110 denotes a metal plate to which the semiconductor chip 130 is connected, and the substrate is generally copper or aluminum. Depending on the solder used, a metal plating (not shown) having good wettability with the solder to be used is formed on the surface of the metal plate 110 in order to improve the bondability. Reference numeral 120 denotes a solder layer for joining the metal plate 110 and the back metal film 132, which is divided into a plurality of solder blocks 122 by a gap 124. There is an oxide film 123a on the side surface of each solder block 122. Here, the solder layer 120 may be any alloy solder containing a metal that easily forms an oxide film on the surface. A typical example is an alloy containing Zn, Sn, and the like. In particular, Zn—Al alloy solder is known to have a strong oxide film on the surface, and is particularly effective in the present invention.

By the way, as will be described in the manufacturing method described later, the gap is not always in contact with the metal plate 110 or the back metal 132 of the semiconductor chip 130 as shown in FIG. That is, as shown in FIG. 2A, the surface of the metal plate 110 facing the gap 124 may get wet with the solder, and on the contrary, although not shown, the front surface of the metal 132 on the back surface of the semiconductor chip is completely soldered. It may get wet. Further, both of the above may occur at the same time as shown in FIG. 2 (b), or this event may occur sparsely as shown in FIG. 2 (c). Even so, if the gap 124 formed according to the procedure described below is inherent in the solder layer 120, even if a crack occurs in a part of the solder layer, there is an effect of suppressing the progress of the crack.

Next, the action of the structure according to the present invention will be described with reference to FIG. FIG. 3A is a cross-sectional view of a conventional joint structure, and FIG. 3B is a cross-sectional view of the same structure as that of FIG. 1, but is drawn with consideration for the difference in the coefficient of thermal expansion between the metal plate 110 and the semiconductor chip 130. It was done. The solder layer 120 in which the back metal 132 of the semiconductor chip 130 and the metal plate 110 are melted at a temperature equal to or higher than the melting point causes an alloying reaction. At this point there is no stress at any interface. However, since the coefficient of thermal expansion of the metal plate 110 is generally larger than that of the semiconductor chip 130, when the temperature of the structure becomes lower than the melting point and the solder layer 120 solidifies to form a bond, and then, for example, the temperature drops to room temperature. Then, the metal plate 110 shrinks more, which causes the solder layer 120 to be deformed as shown in FIG.

At this time, as is clear from the figure, the solder block near the outer peripheral portion receives a larger shearing force than the vicinity near the center of the semiconductor chip. Therefore, when the metal experiences repeated temperature changes, the metal undergoes work hardening, and in the conventional structure of FIG. 3A, cracks occur at the ends of the solder layer 120, particularly at the corners of a square semiconductor chip (not shown), which gradually increases. Progress inward. However, according to the present invention, due to the presence of the gap 124 and the oxide film 123a as shown in FIG. 3B, the solder blocks 122 are not affected by the adjacent solder blocks, and the metal plates to which they are joined are not affected. It receives shearing force only from 110 and the semiconductor chip 130. That is, even if cracks occur in the adjacent solder blocks, propagation does not occur due to the presence of the gaps 124 covered with the oxide film. Therefore, a structure like the present invention can significantly extend its life with repeated temperature changes. Here, the definition of the life is often defined as the time when the electric resistance and the thermal resistance of the semiconductor chip 130 rise to an appropriate value (for example, 10%) due to the growth of cracks in the solder layer 120.

Next, a specific example that brings about the above-mentioned effect will be shown. FIG. 4A is a perspective view of the simplest solder block 122 having a cross-sectional view of FIG. Here, the gap 124 is drawn wider than it really is for ease of understanding. In this case, the first cracks occur at both ends of the solder blocks at both ends, but even in the cracked solder blocks themselves, the stress decreases rapidly when the distance from the corners of the semiconductor chip 130 is small. Therefore, even in the solder blocks at both ends in the figure, cracks do not grow much.

Further, in FIG. 4B, the narrow gap 124 runs vertically and horizontally, and the solder block 122 becomes a columnar shape. With such a configuration, crack growth is minimal.

Looking at FIG. 3B again, the stress received by the solder block 122 near the outer periphery of the semiconductor chip 110 is large, but is slight near the center. Therefore, as shown in FIG. 5, the narrow gap 124 is not provided near the center, the width of the solder block 122 is widened, and the gap between the small gaps 124 is narrowed near the outer circumference to reduce the width of the solder block 122. Keep it narrow. In this way, the thermal conductivity near the center where the density of the heat flow generated from the semiconductor chip 130 is high while suppressing the cracks generated by the shear stress that increases on the outer periphery of the semiconductor chip, especially at the corners, and their growth due to repeated temperature changes. Can be kept high.

FIG. 6A shows a striped solder block structure of FIG. 4A, and FIG. 6B shows a semiconductor chip in which a shear stress due to a temperature change is not so much applied in the columnar solder block structure of FIG. The solder block is greatly widened near the center of 110. Further, the same effect can be obtained even if the gap 124 is formed in a corridor shape as shown in FIG. 6 (c). In this configuration, the solder block 122 near the outer circumference also has an annular shape as shown in the figure. Here, the gap is always in contact with the outside so that the gas trapped inside does not affect the solder block or the like due to the temperature change. Therefore, the one in which the solder block 122 is interrupted as shown in FIG. 6D is also included in this category.

Next, an example of a method for manufacturing the semiconductor device 100 will be described with reference to FIG. 7. First, as shown in FIG. 7A, a preformed solder block 122 is placed on the metal plate 110. As a method for forming the solder block 122, although not particularly shown, there is a method of performing electric discharge machining, high-pressure water cutting, laser cutting, or the like on a plate solder having substantially the same size as the semiconductor chip 130. Oxide films 123a, 123b, and 123c are formed on the side surfaces, the lower surface, and the upper surface of each solder block 122, respectively. This may be one that is naturally oxidized by contact with air, or a separately actively formed oxide film. When arranging these plurality of solder blocks 122 on the metal plate 110, they are arranged as closely as possible so as not to impair the electrical and thermal characteristics of the semiconductor chip. In this method, the distance between the solder blocks 122 can be partially widened, which is effective when it is desired to interpose another structure in the solder layer 120.

Further, the plurality of solder blocks 122 may be previously solidified into one with a binder made of an organic substance, and then arranged on the metal plate 110. In that case, select a binder that completely scatters below the temperature at which the solder layer 120 melts. Alternatively, as shown in FIG. 6A, it is also effective in terms of work efficiency to form the solder block 122 as a continuous structure.

Then, a little pressure is applied from above the arranged solder block 122 and ultrasonic waves are applied to crush the oxide film 123b on the lower surface and the metal oxide film naturally formed on the surface of the metal plate 110 to join the metals together. Let me. The joining at this time may be such that the individual solder blocks 122 are temporarily joined so as not to cause misalignment in the following steps. Further, as this temporary joining method, welding or other joining techniques may be applied as long as the oxide film 123a formed on the side surface of the solder block 122 is maintained.

Further, for the purpose of strengthening the oxide film 122a from this state, an oxidation step such as exposure to a high temperature for a short time in an oxidizing atmosphere such as in the air may be inserted. In particular, when Zn—Al alloy solder is used as the solder layer 120, performing the above operation in air is equivalent to the oxidation step itself. In order to uniformly realize this oxidation, the gap 124 is configured such that one end or both ends thereof communicate with the outside air on the side surface of the solder layer.

Subsequently, as shown in FIG. 7B, the back surface metal film 132 of the semiconductor chip 130 is made to face the upper surface of the plurality of solder blocks 122, a little pressure is applied from above the semiconductor chip 130, and ultrasonic waves are applied. Then, the metal oxide film naturally formed on the surface of the oxide film 123c on the upper surface and the metal film 132 on the back surface is crushed to bond the metals to each other. The joining at this time may be such that the semiconductor chip 110 is temporarily joined to the individual solder blocks 122 in the following steps (temporary joining step). After that, by heating above the melting point of the solder block 122, the molten solder of the solder block 120 causes an alloying reaction with the metal plate 110 and the back metal film 132 of the semiconductor chip 130, and when the temperature becomes lower than the melting point. When the bonding is established and the temperature returns to around room temperature, the structure as shown in FIG. 1 is obtained, and a strong bonding is completed (main bonding step).

Further, the semiconductor device 100 can also be realized by the method shown in FIG. That is, as shown in FIG. 8A, there is also a method in which the plate solder 121 to be the solder layer 120 in the future is temporarily joined to a predetermined position of the metal plate 110 and then formed into the solder block 122. For example, in the case of FIG. 8B, the plate solder 121 is cut by the teeth 141 of the dicing saw attached to the processing head 140. Alternatively, although not shown, a laser beam or an electron beam may be emitted from another processing head 140 to locally melt and remove the solder to obtain the same result as in FIG. 8 (b).

Alternatively, as shown in FIG. 9 (a), the punch 150 having V-shaped teeth is pressed from above the plate solder 121 as shown in FIG. 9 (b) by performing a press working to obtain FIG. 9 (c). The solder block 122 can also be molded as shown. In this case, the gap 122 remains as a V-shaped gap, but if the V-shape has an acute angle, it does not affect the electrical and thermal characteristics of the semiconductor chip 130. According to such press working, a plurality of solder blocks 122 can be formed in a short time, which is suitable for mass production.

Here, as described with reference to FIG. 5, the shape of the solder block 122 may be widened near the center of the semiconductor chip, and when the plate solder 121 is processed in advance and then used, FIG. It may have such a shape. FIG. 10 shows a top view of the plate solder 121 as a precursor to be the solder layer 120. For example, when the semiconductor chip 130 is 5 mm square, prepare a plate solder 121 having the same 5 mm square and a thickness of 200 μm, and use a dicing saw with a tooth width of 50 μm to make only the corners as thin as 250 μm pitch as shown in the figure. It forms a gap 124. A view of the structure completed by using the plate solder 121 by cutting the line segments AA in the drawing corresponds to FIG. Further, when the sheet metal 121 is temporarily bonded to the metal plate 110 and then processed with a dicing saw, a laser configuration, an electron beam or a punch, or the sheet metal 121 alone does not penetrate the groove formed by the dicing saw and is finite. When molding while leaving the thickness, the shape as shown in FIG. 10B may be used.

In addition, in the method of realizing the semiconductor device 100 of the present invention described with reference to FIG. 7 or 8 above, in order to ensure the separation of the solder block 122 on the metal plate side, as shown in FIG. It is possible to apply a process of repelling solder in advance to a place where a gap is desired to be formed. The region 260 in FIG. 11 schematically shows a local region subjected to the treatment as described below. The process of repelling the solder is, for example, a method of forming an oxide film by a chemical treatment at a predetermined portion of the metal plate 110, or a metal having good wettability with the solder used on the surface of the metal plate 110. In the case of plating, there is a method of burning off the plating at a place where a gap is desired to be formed by a laser beam or an electron beam in the future. Alternatively, conversely, there is also a method of locally volume-forming an inorganic oxide that does not allow the solder to get wet at a place where a gap is desired to be formed in the future. This is, for example, a method in which a paste containing fine particles of inorganic oxide is screen-printed and the organic matter of the paste is removed by heating.

In addition, in FIGS. 8 and 9, the process of forming the solder block 122 on the metal plate 110 was first disclosed, but of course, after forming the solder block 122 on the metal electrode 132 of the semiconductor chip 130, The procedure of joining to the metal plate 110 may also be used.

Further, the semiconductor device 100 can be realized by another method. For example, as shown in FIG. 11, a region 260 that has been locally subjected to a soldering process is formed on the metal plate 110. Next, although not shown, as shown in FIGS. 7 (a) and 8 (a), the plate solder 121 is placed and the plate solder 121 is melted once at this stage. Then, as shown in FIG. 12A, the solder avoids the region 260 and solidifies as an island-shaped region 125 of the solder having a substantially hemispherical cross section. By the way, the figure is drawn in a slightly deformed form for explanation. After that, the surface oxidation treatment of the island-shaped region 125 of the solder was performed, and then the same solder repelling treatment was performed on the front surface of the back metal film 132 of the semiconductor chip 130 in advance as shown in FIG. 12 (b). The region 261 is formed, placed on the solder block 122 and pressurized to break the front surface oxide film, and is heated to be bonded to the back surface metal film 132. Then, the solder block 122 is self-aligned and the structure shown in FIG. 1 is obtained. Alternatively, although not shown in the middle, the side surface shape can be made concave as shown in FIG. 12C when the solder is solidified by devising a device for controlling the thickness of the solder block 122 while the solder is melting. This shape is known as a shape that is resistant to stress in solder bumps and the like.

As a device for controlling the thickness of the solder block 122, for example, several balls made of an inorganic substance that does not react with the molten solder are interposed between the metal plate 110 and the semiconductor chip 130. That is, first, at room temperature, the back metal film 132 of the semiconductor chip 130 is brought into contact with the island-shaped region 125 of the solder from FIG. 12B. In this state, the intervening balls are assumed to be shorter than the island-shaped region 125 of the solder. Next, when the temperature of the entire structure is raised to a temperature equal to or higher than the melting point of the solder while slightly applying pressure from above the semiconductor chip 130, the oxide film on the surface of the island-shaped region 125 of the solder in contact with the back metal film 132 is broken, and the molten solder is made of the back metal. It spreads wet on the film 132 side. As a result, the distance between the metal plate 110 and the semiconductor chip 130 tends to be shortened, but if the shrinkage is prevented by interposing the ball of an appropriate size here, the molten solder wets and spreads to the back surface metal film 132 side. Since the solder volume is used, the side surface shape of the solder block 122 at the time of solidification can be made concave.

Although specific embodiments of the semiconductor device according to the present invention and modifications based on the same have been described above, the present invention is not necessarily limited to these, and the invention is carried out without departing from the scope of claims of the present invention. All the configurations made are included in the scope of the present invention.

100 Semiconductor device 110 Metal substrate 120 Solder layer 121 Plate solder 122 Solder block 123a, 123b, 123c Oxidation film 124 Gap 125 Solder island-shaped area 130 Semiconductor chip 132 Back surface metal film 140 Processing head 141 Dicing saw tooth 150 Punch 260, 261 Solder-repelled area

Claims (14)

A semiconductor device in which a metal electrode formed on one main surface of a semiconductor chip and a metal plate are joined by a solder layer.
The solder layer has a plurality of gaps extending in the direction from the metal electrode to the metal plate.
Both sides of the solder layer facing each other through the gap are covered with an oxide film.
A semiconductor device characterized by this. The semiconductor device according to claim 1, wherein the solder layer is made of a Zn—Al alloy. The semiconductor device according to claim 1, wherein the plurality of gaps in the solder layer run in parallel with each other at least partially to form a striped shape. The semiconductor device according to claim 1, wherein the plurality of gaps in the solder layer intersect vertically and horizontally at least partially to form a network. The semiconductor device according to claim 1, wherein the plurality of gaps in the solder layer form a substantially corridor shape at least in the vicinity of the outer periphery of the semiconductor chip. The invention according to any one of claims 3 to 5, wherein the distance between the plurality of fine gaps in the solder layer is narrower near the outer periphery than near the center of the semiconductor chip. Semiconductor equipment. The solder layer that joins a semiconductor chip having a metal electrode on one main surface and a metal plate has a plurality of gaps extending in the direction from the semiconductor chip to the metal plate, and faces each other through the gaps. A method for manufacturing a semiconductor device having an oxide film on both side surfaces of the solder layer.
A temporary joining step of arranging a plurality of block-shaped solders on the surface of the metal plate and temporarily joining them.
An oxidation step that oxidizes the surface of the block-shaped solder,
A main joining step in which the block-shaped solder and the metal electrode of the semiconductor chip are in contact with each other, heated to a temperature equal to or higher than the melting point of the block-shaped solder, and then cooled to join the whole.
A method for manufacturing a semiconductor device, which comprises at least. The solder layer that joins a semiconductor chip having a metal electrode on one main surface and a metal plate has a plurality of gaps extending in the direction from the semiconductor chip to the metal plate, and faces each other through the gaps. A method for manufacturing a semiconductor device having an oxide film on both side surfaces of the solder layer.
A temporary joining process in which plate solder is placed on the surface of the metal plate and temporarily joined.
A molding process for processing the gaps in the fixed plate solder, and
An oxidation step that oxidizes the surface of the molded plate solder,
A main joining step in which the molded plate solder and the metal electrode of the semiconductor chip are in contact with each other, heated to a temperature equal to or higher than the melting point of the molded plate solder, and then cooled to join the whole.
A method for manufacturing a semiconductor device, which comprises at least. The solder layer that joins the metal electrode and the metal plate formed on one main surface of the semiconductor chip has a plurality of gaps extending in the direction from the semiconductor chip to the metal plate, and the solder layers extend through the gaps. A method for manufacturing a semiconductor device having an oxide film on both side surfaces of the solder layers facing each other.
A reforming step of making the region on the surface of the metal plate where the gaps should be formed into a property of repelling molten solder,
A temporary joining process in which plate solder is placed on the surface of the metal plate and temporarily joined.
An island forming step of melting the sheet metal, forming solder islands in a region of the metal plate not subjected to the reforming treatment, and cooling and solidifying the solder islands.
An oxidation step that oxidizes the surface of the molded solder islands,
In this joining step, in which the solder islands and the metal electrodes of the semiconductor chip are in contact with each other, the solder islands are heated to a temperature equal to or higher than the melting point, and then cooled to join the whole.
A method for manufacturing a semiconductor device, which comprises at least. A reforming step of making the region on the surface of the metal plate where the gap should be formed into a property of repelling molten solder
The method for manufacturing a semiconductor device according to claim 7 or 8, wherein the semiconductor device is manufactured. A metal electrode reforming treatment step of performing a treatment of repelling molten solder in a region on the surface of the metal electrode of the semiconductor chip where the gap should be formed is included.
The method for manufacturing a semiconductor device according to any one of claims 7 to 9, wherein the semiconductor device is manufactured. The reforming treatment step and the metal electrode reforming treatment step are treatments for locally oxidizing the metal surface.
The method for manufacturing a semiconductor device according to any one of claims 9 to 11, wherein the semiconductor device is manufactured. The modification treatment step and the metal electrode modification treatment step are processes for removing a part of the surface metal having good wettability to molten solder, which is formed in advance on the surface of the metal electrode or the surface of the metal plate. ,
The method for manufacturing a semiconductor device according to any one of claims 9 to 11, wherein the semiconductor device is manufactured. The reforming treatment step and the metal electrode reforming treatment step are treatments for locally depositing an oxide film that repels molten solder.
The method for manufacturing a semiconductor device according to any one of claims 9 to 11, wherein the semiconductor device is manufactured.

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