JP2020136431A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP2020136431A
JP2020136431A JP2019026521A JP2019026521A JP2020136431A JP 2020136431 A JP2020136431 A JP 2020136431A JP 2019026521 A JP2019026521 A JP 2019026521A JP 2019026521 A JP2019026521 A JP 2019026521A JP 2020136431 A JP2020136431 A JP 2020136431A
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semiconductor chip
substrate
semiconductor
groove
semiconductor device
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かほり 蕨
Kahori Warabi
かほり 蕨
古山　英人
Hideto Furuyama
英人 古山
和哉 大平
Kazuya Ohira
和哉 大平
栗田　洋一郎
Yoichiro Kurita
洋一郎 栗田
浩 上村
Hiroshi Kamimura
浩 上村
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Toshiba Corp
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Toshiba Corp
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Abstract

To prevent the peeling of a semiconductor chip due to trapping of air bubbles between a substrate and a semiconductor chip even when the semiconductor chip bonded to the substrate is warped.SOLUTION: A semiconductor device manufacturing method includes a step of forming a groove on the main surface of a substrate, and a step of bonding the semiconductor chip to the main surface of the substrate such that the groove crosses the edge of the semiconductor chip.SELECTED DRAWING: Figure 3

Description

本発明の実施形態は、半導体デバイスの製造方法および半導体デバイスに関する。 Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a semiconductor device.

ウェーハ同士の接合により基板上に例えば光デバイスを形成する場合、半導体（化合物半導体）が必要な発光素子や受光素子が形成される部分以外の、基板上で大部分を占める光配線部等を形成する領域に接合された半導体は除去され、半導体材料の利用効率が悪い。この問題を解決する技術として、必要な部分にのみ且つ狙った位置に対する位置ずれを小さくして、半導体チップを基板に接合するＣｏＷ（Chip on Wafer）接合技術がある。 When, for example, an optical device is formed on a substrate by joining wafers to each other, an optical wiring portion or the like that occupies most of the substrate is formed other than a portion where a light emitting element or a light receiving element that requires a semiconductor (compound semiconductor) is formed. The semiconductor bonded to the region is removed, and the utilization efficiency of the semiconductor material is poor. As a technique for solving this problem, there is a CoW (Chip on Wafer) bonding technique for bonding a semiconductor chip to a substrate only in a necessary part and with a small displacement with respect to a target position.

米国特許出願公開第２０１５／０２８８１４６号明細書U.S. Patent Application Publication No. 2015/0288146

本発明の実施形態は、基板に接合される半導体チップに反りが生じても、基板と半導体チップとの間に気泡が閉じ込められることによる半導体チップの剥がれを防止することを目的とする。 An object of the present invention is to prevent the semiconductor chip from peeling off due to trapping of air bubbles between the substrate and the semiconductor chip even if the semiconductor chip bonded to the substrate is warped.

本発明の実施形態によれば、半導体デバイスの製造方法は、基板の主面に溝を形成する工程と、前記溝が半導体チップのエッジを横切るように、前記半導体チップを前記基板の前記主面に接合する工程と、を有する。 According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes a step of forming a groove on a main surface of a substrate and a process of forming the semiconductor chip on the main surface of the substrate so that the groove crosses an edge of the semiconductor chip. It has a step of joining to.

実施形態に係る半導体デバイスの製造方法を示す模式斜視図である。It is a schematic perspective view which shows the manufacturing method of the semiconductor device which concerns on embodiment. 実施形態に係る半導体デバイスの製造方法を示す模式平面図である。It is a schematic plan view which shows the manufacturing method of the semiconductor device which concerns on embodiment. 実施形態に係る半導体デバイスの製造方法を示す模式平面図である。It is a schematic plan view which shows the manufacturing method of the semiconductor device which concerns on embodiment. 実施形態に係る半導体デバイスの製造方法を示す模式平面図である。It is a schematic plan view which shows the manufacturing method of the semiconductor device which concerns on embodiment. （ａ）は図３におけるＡ−Ａ断面図であり、（ｂ）は図４におけるＢ−Ｂ断面図である。(A) is a sectional view taken along the line AA in FIG. 3, and FIG. 4B is a sectional view taken along the line BB in FIG. （ａ）及び（ｂ）は、実施形態に係る半導体デバイスの模式平面図である。(A) and (b) are schematic plan views of the semiconductor device according to the embodiment. 実施形態に係る半導体デバイスの製造方法を示す模式平面図である。It is a schematic plan view which shows the manufacturing method of the semiconductor device which concerns on embodiment. 実施形態に係る半導体デバイスの製造方法を示す模式平面図である。It is a schematic plan view which shows the manufacturing method of the semiconductor device which concerns on embodiment. 図８におけるＣ−Ｃ断面図である。FIG. 8 is a sectional view taken along line CC in FIG. 実施形態に係る半導体デバイスの製造方法を示す模式平面図である。It is a schematic plan view which shows the manufacturing method of the semiconductor device which concerns on embodiment. 実施形態に係る半導体デバイスを用いた光集積回路の模式図である。It is a schematic diagram of the optical integrated circuit using the semiconductor device which concerns on embodiment. （ａ）は実施形態に係る半導体デバイスの模式平面図であり、（ｂ）は図１２（ａ）におけるＤ−Ｄ断面図である。(A) is a schematic plan view of the semiconductor device according to the embodiment, and (b) is a sectional view taken along line DD in FIG. 12 (a). 反りをもつ半導体チップのＣｏＷ接合を示す模式断面図である。It is a schematic cross-sectional view which shows the CoW junction of the semiconductor chip which has a warp. （ａ）及び（ｂ）は、参考例の半導体デバイスの製造方法を示す模式平面図である。(A) and (b) are schematic plan views which show the manufacturing method of the semiconductor device of a reference example.

以下、適宜図面を参照しながら実施形態の説明を行っていく。説明の便宜のため、各図面の縮尺は必ずしも正確ではなく、相対的な位置関係などで示す場合がある。また、同一または同様の要素には、同じ符号を付している。 Hereinafter, embodiments will be described with reference to the drawings as appropriate. For convenience of explanation, the scale of each drawing is not always accurate and may be indicated by relative positional relationships. The same or similar elements are designated by the same reference numerals.

図１３は、反りをもつ半導体チップ３０のＣｏＷ接合を示す模式断面図である。 FIG. 13 is a schematic cross-sectional view showing a CoW junction of the semiconductor chip 30 having a warp.

接合対象の基板１０の主面１１に対して、半導体チップ３０の中央部が凸状になる反りを半導体チップ３０がもつ場合、半導体チップ３０の端部が中央部よりも先に基板１０に接合され、基板１０と半導体チップ３０との間に空気５０が閉じ込められることとなる。その結果、接合面に気泡が入り、半導体チップ３０が剥がれてしまう原因になり得る。 When the semiconductor chip 30 has a warp in which the central portion of the semiconductor chip 30 is convex with respect to the main surface 11 of the substrate 10 to be bonded, the end portion of the semiconductor chip 30 is bonded to the substrate 10 before the central portion. Then, the air 50 is confined between the substrate 10 and the semiconductor chip 30. As a result, air bubbles may enter the joint surface, which may cause the semiconductor chip 30 to peel off.

そこで、図１４（ａ）に示すように、例えば格子状の溝１２を基板１０の主面１１に形成し、その溝１２に半導体チップ３０を重ねて接合する。溝１２が半導体チップ３０のエッジ３０ｅを横切るようにすることで、接合面の気泡を溝１２を通じて半導体チップ３０の外側に逃がすことができる。 Therefore, as shown in FIG. 14A, for example, a grid-like groove 12 is formed on the main surface 11 of the substrate 10, and the semiconductor chip 30 is overlapped and joined to the groove 12. By allowing the groove 12 to cross the edge 30e of the semiconductor chip 30, air bubbles on the joint surface can escape to the outside of the semiconductor chip 30 through the groove 12.

半導体チップ３０において溝１２の上の部分は基板１０によって支えられていないため、溝１２が形成された領域には素子や配線を形成することが難しい。すなわち、図１４（ｂ）に示すように、基板１０に接合された半導体チップ３０から素子３０ａを作製可能な領域は、半導体チップ３０を接合した領域のうち、溝１２を除く領域となり、非連続の狭い領域となってしまう。また、素子３０ａと素子３０ａとの間に溝１２があることで、素子３０ａ間の配線の形成も困難である。 Since the upper portion of the groove 12 in the semiconductor chip 30 is not supported by the substrate 10, it is difficult to form an element or wiring in the region where the groove 12 is formed. That is, as shown in FIG. 14B, the region in which the element 30a can be manufactured from the semiconductor chip 30 bonded to the substrate 10 is a region in which the semiconductor chip 30 is bonded, excluding the groove 12, and is discontinuous. It becomes a narrow area of. Further, since the groove 12 is provided between the element 30a and the element 30a, it is difficult to form the wiring between the elements 30a.

そこで、本発明の実施形態によれば、半導体チップの剥がれを防止し、さらに広いデバイス作製可能エリアを確保するためのＣｏＷ接合方法を提供する。 Therefore, according to the embodiment of the present invention, there is provided a CoW joining method for preventing the semiconductor chip from peeling off and securing a wider device manufacturing area.

図１は、実施形態に係る半導体デバイスの製造方法を示す模式斜視図である。 FIG. 1 is a schematic perspective view showing a method of manufacturing a semiconductor device according to an embodiment.

半導体ウェーハ２０上で個片化された半導体チップ３０を、後述するように溝が形成されたウェーハ状態の基板１０の主面１１における必要な位置に接合する。複数の半導体チップ３０を基板１０に接合した後、基板１０上で半導体チップ３０を加工し、必要に応じて電極や絶縁膜を形成して、基板１０上に複数の素子３０ａを形成する。さらに、基板１０上に素子３０ａ間を接続する配線が形成される。 The semiconductor chips 30 fragmented on the semiconductor wafer 20 are joined to the required positions on the main surface 11 of the wafer-state substrate 10 in which grooves are formed, as will be described later. After joining the plurality of semiconductor chips 30 to the substrate 10, the semiconductor chips 30 are processed on the substrate 10, electrodes and insulating films are formed as needed, and the plurality of elements 30a are formed on the substrate 10. Further, a wiring for connecting the elements 30a is formed on the substrate 10.

図２〜図４は、溝付き基板に半導体チップを接合し、その半導体チップから素子を形成する工程を表す模式断面図である。 2 to 4 are schematic cross-sectional views showing a process of joining a semiconductor chip to a grooved substrate and forming an element from the semiconductor chip.

図２に示すように、基板１０の主面１１に溝１２が形成される。基板１０は、例えばシリコン基板である。または、基板１０はガラス基板であってもよい。 As shown in FIG. 2, a groove 12 is formed on the main surface 11 of the substrate 10. The substrate 10 is, for example, a silicon substrate. Alternatively, the substrate 10 may be a glass substrate.

例えば、基板１０の主面１１上で互いに直交する方向に延びる複数の溝１２が形成される。 For example, a plurality of grooves 12 extending in directions orthogonal to each other are formed on the main surface 11 of the substrate 10.

このような溝１２が形成された基板１０の主面１１に対して、図３に示すように、半導体チップ３０を接合する。図５（ａ）は、図３におけるＡ−Ａ断面図である。 As shown in FIG. 3, the semiconductor chip 30 is bonded to the main surface 11 of the substrate 10 on which the groove 12 is formed. FIG. 5A is a cross-sectional view taken along the line AA in FIG.

半導体チップ３０は、例えば化合物半導体の材料層である。化合物半導体は、例えばIII-V族半導体である。 The semiconductor chip 30 is, for example, a material layer of a compound semiconductor. The compound semiconductor is, for example, a group III-V semiconductor.

図３に示すように、複数の半導体チップ３０が基板１０の主面１１に接合される。１つの半導体チップ３０が主面１１に接合された領域を素子領域１５とする。主面１１に複数の素子領域１５が形成される。 As shown in FIG. 3, a plurality of semiconductor chips 30 are bonded to the main surface 11 of the substrate 10. The region where one semiconductor chip 30 is joined to the main surface 11 is defined as the element region 15. A plurality of element regions 15 are formed on the main surface 11.

半導体チップ３０は４つのエッジ（または辺）３０ｅをもつ四角形状の平面形状を有する。そのエッジ３０ｅを溝１２が横切るように、半導体チップ３０は溝１２に重ねられる。図３に示す例では、４つの溝１２がそれぞれ半導体チップ３０の４つのエッジ３０ｅに沿って、半導体チップ３０の下に重なっている。 The semiconductor chip 30 has a quadrangular planar shape having four edges (or sides) 30e. The semiconductor chip 30 is superposed on the groove 12 so that the groove 12 crosses the edge 30e. In the example shown in FIG. 3, the four grooves 12 are overlapped under the semiconductor chip 30 along the four edges 30e of the semiconductor chip 30, respectively.

１つの半導体チップ３０が重なる１つの素子領域１５において、溝１２の内側の領域は溝で分割されていない。１つの半導体チップ３０において、溝１２の内側の領域に重なる部分の面積は、溝１２の外側に重なる部分の面積よりも広い。 In one element region 15 on which one semiconductor chip 30 overlaps, the region inside the groove 12 is not divided by the groove. In one semiconductor chip 30, the area of the portion overlapping the inner region of the groove 12 is larger than the area of the portion overlapping the outer region of the groove 12.

溝１２は半導体チップ３０の下に重なる素子領域１５で交差している。溝１２の交点と半導体チップ３０の角３０ｃとの間の距離ｄ２は、溝１２の交点と半導体チップ３０の中心Ｃとの間の距離ｄ１よりも短い。すなわち、溝１２の交点は、半導体チップ３０の中心Ｃよりも角３０ｃの近くに位置する。 The grooves 12 intersect at an overlapping element region 15 under the semiconductor chip 30. The distance d2 between the intersection of the grooves 12 and the corner 30c of the semiconductor chip 30 is shorter than the distance d1 between the intersection of the grooves 12 and the center C of the semiconductor chip 30. That is, the intersection of the grooves 12 is located closer to the angle 30c than the center C of the semiconductor chip 30.

図３に示す例では、交点と交点とを結ぶ溝１２は、半導体チップ３０のエッジ３０ｅの近傍でエッジ３０ｅに沿って延びている。または、交点と交点とを結ぶ溝１２は屈曲や蛇行していてもよい。 In the example shown in FIG. 3, the groove 12 connecting the intersections extends along the edge 30e in the vicinity of the edge 30e of the semiconductor chip 30. Alternatively, the groove 12 connecting the intersections may be bent or meandering.

溝１２は、交点から半導体チップ３０のエッジ３０ｅを横切って半導体チップ３０の外側に延びている。このため、半導体チップ３０が図１３に示すように凸状に沿っていても接合面に生じる気泡を溝１２を通じて半導体チップ３０の外側に逃がすことができる。半導体チップ３０と基板１０の主面１１との間に気泡が閉じ込められず、半導体チップ３０の剥がれを防ぐことができる。 The groove 12 extends from the intersection to the outside of the semiconductor chip 30 across the edge 30e of the semiconductor chip 30. Therefore, even if the semiconductor chip 30 follows a convex shape as shown in FIG. 13, air bubbles generated on the joint surface can escape to the outside of the semiconductor chip 30 through the groove 12. Bubbles are not trapped between the semiconductor chip 30 and the main surface 11 of the substrate 10, and the semiconductor chip 30 can be prevented from peeling off.

また、１つの半導体チップ３０に対して、そのエッジ３０ｅの近くに溝１２を制限することで、溝１２の内側に、素子を形成できる領域を広く連続的に確保することができる。 Further, by limiting the groove 12 near the edge 30e of one semiconductor chip 30, it is possible to continuously and widely secure a region in which the element can be formed inside the groove 12.

基板１０の主面１１に接合された半導体チップ３０から、図４に示すように、基板１０上に素子３０ａが形成される。図５（ｂ）は、図４におけるＢ−Ｂ断面図である。 As shown in FIG. 4, the element 30a is formed on the substrate 10 from the semiconductor chip 30 bonded to the main surface 11 of the substrate 10. FIG. 5B is a cross-sectional view taken along the line BB in FIG.

素子３０ａは、例えば光素子である。ある素子領域１５の半導体チップ３０からは発光素子を形成することができ、別の素子領域１５の半導体チップ３０からは受光素子を形成することができる。同一の半導体チップ３０（例えばIII-V族半導体エピタキシャル成長層）を用いて、同じ基板１０上で発光素子も受光素子も形成できる。これは、材料および工程の削減を可能にする。 The element 30a is, for example, an optical element. A light emitting element can be formed from the semiconductor chip 30 in one element region 15, and a light receiving element can be formed from the semiconductor chip 30 in another element region 15. Using the same semiconductor chip 30 (for example, a III-V semiconductor epitaxial growth layer), both a light emitting element and a light receiving element can be formed on the same substrate 10. This allows for material and process reductions.

１つの半導体チップ３０から複数の素子３０ａが形成される。基板１０の主面１１に接合された半導体チップ３０において、素子３０ａ以外の部分は除去される。図４に示す例では、半導体チップ３０において、溝１２の外側の領域に接合された部分は除去される。また、半導体チップ３０において溝１２の上の部分も除去される。 A plurality of elements 30a are formed from one semiconductor chip 30. In the semiconductor chip 30 bonded to the main surface 11 of the substrate 10, the portion other than the element 30a is removed. In the example shown in FIG. 4, in the semiconductor chip 30, the portion joined to the region outside the groove 12 is removed. Further, the portion above the groove 12 in the semiconductor chip 30 is also removed.

溝１２は、連続した閉じたパターンであることに限らない。例えば、図６（ａ）に示すように、隣り合う素子領域１５における隣り合う溝１２に非連続部（溝１２がない部分）１３を形成することで、隣り合う素子領域１５の素子同士を配線で接続することができる。 The groove 12 is not limited to a continuous closed pattern. For example, as shown in FIG. 6A, by forming a discontinuous portion (a portion without the groove 12) 13 in the adjacent grooves 12 in the adjacent element regions 15, the elements in the adjacent element regions 15 are wired to each other. You can connect with.

図６（ａ）に示す例では、２つの素子領域１５のうち一方にはＬＤ(Laser Diode)３２が形成され、他方にはＰＤ(Photo Detector)３３が形成され、それらＬＤ３２とＰＤ３３とを接続する光導波路３５が溝１２の非連続部１３を通って基板１０上に形成されている。 In the example shown in FIG. 6A, an LD (Laser Diode) 32 is formed in one of the two element regions 15, and a PD (Photo Detector) 33 is formed in the other, and the LD 32 and the PD 33 are connected to each other. An optical waveguide 35 is formed on the substrate 10 through the discontinuous portion 13 of the groove 12.

また、図６（ｂ）に示すように、前述したように主面１１に接合された半導体チップ３０において、溝１２の外側の領域にも半導体層を部分的に残して、素子（この例では、ＬＤ３２やＰＤ３３）を形成してもよい。 Further, as shown in FIG. 6B, in the semiconductor chip 30 bonded to the main surface 11 as described above, the semiconductor layer is partially left in the region outside the groove 12, and the element (in this example, in this example). , LD32 and PD33) may be formed.

図７は、基板１０の主面１１に形成した溝１２の他のレイアウトを示す模式平面図である。 FIG. 7 is a schematic plan view showing another layout of the groove 12 formed on the main surface 11 of the substrate 10.

半導体チップ３０の４つの角３０ｃの近くに、十字状の溝１２が配置されている。この場合においても、溝１２は半導体チップ３０の下に重なる領域からエッジ３０ｅを横切って半導体チップ３０の外側に延びているため、接合面に生じる気泡を溝１２を通じて半導体チップ３０の外側に逃がすことができる。また、１つの半導体チップ３０に対して、その角３０ｃの近くに溝１２を制限することで、素子を形成可能な領域を広く連続的に確保することができる。 A cross-shaped groove 12 is arranged near the four corners 30c of the semiconductor chip 30. Also in this case, since the groove 12 extends from the region overlapping under the semiconductor chip 30 to the outside of the semiconductor chip 30 across the edge 30e, air bubbles generated on the joint surface are allowed to escape to the outside of the semiconductor chip 30 through the groove 12. Can be done. Further, by limiting the groove 12 near the angle 30c of one semiconductor chip 30, it is possible to continuously secure a wide region in which an element can be formed.

図８は、溝を基板にではなく半導体チップに形成した例の模式平面図である。図９は、図８におけるＣ−Ｃ断面図である。 FIG. 8 is a schematic plan view of an example in which a groove is formed not on a substrate but on a semiconductor chip. FIG. 9 is a cross-sectional view taken along the line CC in FIG.

半導体チップ３０における基板１０に対する接合面に、溝４１が形成されている。溝４１は、半導体チップ３０のエッジ３０ｅまで延びている。溝４１の端がエッジ３０ｅに開口している。例えば、溝４１は半導体チップ３０の４つのエッジ３０ｅの近くでエッジ３０ｅに沿って延びている。 A groove 41 is formed on the bonding surface of the semiconductor chip 30 with respect to the substrate 10. The groove 41 extends to the edge 30e of the semiconductor chip 30. The end of the groove 41 is open to the edge 30e. For example, the groove 41 extends along the edge 30e near the four edges 30e of the semiconductor chip 30.

半導体チップ３０の溝４１が形成された面が基板１０の主面１１に接合され、溝４１の内側の領域（溝４１で囲まれた領域）の半導体チップ３０から、図１０に示すように、素子３０ａが基板１０上に形成される。この例では、半導体チップ３０において溝４１の外側の部分、および溝４１が形成された部分は除去される。 The surface of the semiconductor chip 30 on which the groove 41 is formed is joined to the main surface 11 of the substrate 10, and from the semiconductor chip 30 in the region inside the groove 41 (the region surrounded by the groove 41), as shown in FIG. The element 30a is formed on the substrate 10. In this example, the outer portion of the groove 41 and the portion where the groove 41 is formed in the semiconductor chip 30 are removed.

溝４１は半導体チップ３０の下に重なる領域からエッジ３０ｅまで延びているため、接合面に生じる気泡を溝４１を通じて半導体チップ３０の外側に逃がすことができる。また、１つの半導体チップ３０に対して、そのエッジ３０ｅおよび角３０ｃの近くに溝４１を制限することで、素子を形成可能な領域を広く連続的に確保することができる。 Since the groove 41 extends from the region overlapping under the semiconductor chip 30 to the edge 30e, air bubbles generated on the joint surface can be released to the outside of the semiconductor chip 30 through the groove 41. Further, by limiting the groove 41 near the edge 30e and the angle 30c of one semiconductor chip 30, it is possible to continuously secure a wide region in which an element can be formed.

以上説明したＣｏＷ接合技術は、図１１に示す例えばトランシーバなどの光集積回路に応用することができる。 The CoW bonding technique described above can be applied to an optical integrated circuit such as a transceiver shown in FIG.

前述した溝１２が形成された基板１０上に半導体チップ３０を用いてＬＤ３２とＰＤ３３を形成する。ＬＤ３２とＰＤ３３はそれぞれ、基板１０の主面１１における複数の溝１２の間の領域に設けられている。 The LD32 and PD33 are formed on the substrate 10 on which the groove 12 is formed as described above by using the semiconductor chip 30. The LD32 and PD33 are each provided in the region between the plurality of grooves 12 on the main surface 11 of the substrate 10.

基板１０上には、ＬＤ３２とＰＤ３３を含むSi-optical回路６０と、ＣＭＯＳ回路８０が形成されている。Si-optical回路６０は、その他に、ＳＳＣ(Spot Size Converter)６２、フィルター６３、光変調器６１、光導波路３５を有する。光導波路３５は、溝１２が途切れた非連続部を横切っている。 A Si-optical circuit 60 including LD32 and PD33 and a CMOS circuit 80 are formed on the substrate 10. The Si-optical circuit 60 also includes an SSC (Spot Size Converter) 62, a filter 63, an optical modulator 61, and an optical waveguide 35. The optical fiber optic fiber 35 crosses a discontinuous portion where the groove 12 is interrupted.

ＬＤ３２から出力された光は光変調器６１により変調されて、ＳＳＣ６２により基板１０の外へ出力される。光は導波路３５を伝搬する。受信側は、ＳＳＣ６２から基板１０内に光が入力され、フィルター６３を通り、ＰＤ３３で検出される。ＬＤ３２、ＰＤ３３、および光変調器６１は、電気配線６４でＣＭＯＳ回路８０と接続され、ＣＭＯＳ回路８０の電気信号によって動作制御される。 The light output from the LD 32 is modulated by the light modulator 61 and output to the outside of the substrate 10 by the SSC 62. Light propagates through the waveguide 35. On the receiving side, light is input from the SSC 62 into the substrate 10, passes through the filter 63, and is detected by the PD 33. The LD32, PD33, and optical modulator 61 are connected to the CMOS circuit 80 by the electrical wiring 64, and the operation is controlled by the electrical signal of the CMOS circuit 80.

基板１０に接合される半導体チップ３０としては、半導体材料層のみの構造に限らず、半導体層に電極や絶縁膜が形成された構造でもよい。 The semiconductor chip 30 bonded to the substrate 10 is not limited to a structure consisting only of a semiconductor material layer, and may have a structure in which an electrode or an insulating film is formed on the semiconductor layer.

図１２（ａ）は、実施形態に係る半導体デバイスの他の例の模式平面図であり、（ｂ）は、図１２（ａ）におけるＤ−Ｄ断面図である。図１２（ａ）において、前述した半導体チップ３０が接合された素子領域１５を２点鎖線で表す。 12 (a) is a schematic plan view of another example of the semiconductor device according to the embodiment, and FIG. 12 (b) is a sectional view taken along line DD in FIG. 12 (a). In FIG. 12A, the element region 15 to which the above-mentioned semiconductor chip 30 is bonded is represented by a chain double-dashed line.

この例においても、溝１２が素子領域１５から半導体チップ３０のエッジ３０ｅを横切って半導体チップ３０の外側に延びている。このため、半導体チップ３０が凸状に沿っていても接合面に生じる気泡を溝１２を通じて半導体チップ３０の外側に逃がすことができる。 Also in this example, the groove 12 extends from the element region 15 across the edge 30e of the semiconductor chip 30 to the outside of the semiconductor chip 30. Therefore, even if the semiconductor chip 30 is along the convex shape, air bubbles generated on the joint surface can be released to the outside of the semiconductor chip 30 through the groove 12.

この例のように、溝１２は屈曲していてもよい。また、素子３０ａは、溝１２をまたぐように形成してもよい。 As in this example, the groove 12 may be bent. Further, the element 30a may be formed so as to straddle the groove 12.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

１０…基板、１１…主面、１２…溝、１５…素子領域、２０…半導体ウェーハ、３０…半導体チップ、３０ａ…素子、３２…発光素子、３３…受光素子、３５…光導波路 10 ... substrate, 11 ... main surface, 12 ... groove, 15 ... element region, 20 ... semiconductor wafer, 30 ... semiconductor chip, 30a ... element, 32 ... light emitting element, 33 ... light receiving element, 35 ... optical waveguide

Claims (11)

基板の主面に溝を形成する工程と、
前記溝が半導体チップのエッジを横切るように、前記半導体チップを前記基板の前記主面に接合する工程と、
を有する半導体デバイスの製造方法。 The process of forming a groove on the main surface of the substrate and
A step of joining the semiconductor chip to the main surface of the substrate so that the groove crosses the edge of the semiconductor chip.
A method for manufacturing a semiconductor device having. 複数の前記溝が、前記半導体チップに重なる領域で交差し、
前記複数の溝の交点と前記半導体チップの角との間の距離は、前記複数の溝の交点と前記半導体チップの中心との間の距離よりも短い請求項１記載の半導体デバイスの製造方法。 The plurality of grooves intersect at a region overlapping the semiconductor chip,
The method for manufacturing a semiconductor device according to claim 1, wherein the distance between the intersection of the plurality of grooves and the corner of the semiconductor chip is shorter than the distance between the intersection of the plurality of grooves and the center of the semiconductor chip. 複数の前記半導体チップが、前記基板の前記主面に接合される請求項１または２に記載の半導体デバイスの製造方法。 The method for manufacturing a semiconductor device according to claim 1 or 2, wherein a plurality of the semiconductor chips are bonded to the main surface of the substrate. 複数の前記半導体チップが前記基板の前記主面に接合された複数の素子領域における隣り合う溝に非連続部がある請求項３記載の半導体デバイスの製造方法。 The method for manufacturing a semiconductor device according to claim 3, wherein the plurality of semiconductor chips have discontinuous portions in adjacent grooves in a plurality of element regions bonded to the main surface of the substrate. 前記半導体チップは半導体層を含み、
前記半導体チップを前記基板に接合した後、前記素子領域に前記半導体層を含む素子を形成し、前記半導体層における前記素子以外の部分を除去する請求項３記載の半導体デバイスの製造方法。 The semiconductor chip includes a semiconductor layer and includes a semiconductor layer.
The method for manufacturing a semiconductor device according to claim 3, wherein after the semiconductor chip is bonded to the substrate, an element including the semiconductor layer is formed in the element region, and a portion of the semiconductor layer other than the element is removed. 前記半導体層は化合物半導体層であり、
前記素子は光素子である請求項５記載の半導体デバイスの製造方法。 The semiconductor layer is a compound semiconductor layer.
The method for manufacturing a semiconductor device according to claim 5, wherein the element is an optical element. 複数の前記半導体チップが前記基板の前記主面に接合された複数の素子領域における隣り合う溝に非連続部があり、
前記非連続部に、前記光素子と接続する光導波路を形成する請求項６記載の半導体デバイスの製造方法。 There is a discontinuous portion in the adjacent groove in the plurality of element regions in which the plurality of semiconductor chips are joined to the main surface of the substrate.
The method for manufacturing a semiconductor device according to claim 6, wherein an optical waveguide connected to the optical element is formed in the discontinuous portion. エッジまで延びる溝を有する半導体チップにおける前記溝が形成された面を、基板の主面に接合する工程を有する半導体デバイスの製造方法。 A method for manufacturing a semiconductor device, which comprises a step of joining a surface of a semiconductor chip having a groove extending to an edge to the main surface of a substrate. 主面と、前記主面に形成された複数の溝とを有する基板と、
前記主面における前記複数の溝の間の領域に設けられた半導体層を含む素子と、
を備えた半導体デバイス。 A substrate having a main surface and a plurality of grooves formed on the main surface,
An element including a semiconductor layer provided in a region between the plurality of grooves on the main surface, and
Semiconductor device equipped with. 前記半導体層は化合物半導体層であり、
前記素子は光素子である請求項９記載の半導体デバイス。 The semiconductor layer is a compound semiconductor layer.
The semiconductor device according to claim 9, wherein the element is an optical element. 隣り合う前記溝に非連続部が形成され、
前記非連続部に、前記光素子と接続する光導波路が設けられた請求項１０記載の半導体デバイス。 A discontinuous portion is formed in the adjacent grooves,
The semiconductor device according to claim 10, wherein an optical waveguide connected to the optical element is provided in the discontinuous portion.
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