JPS54150973A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54150973A
JPS54150973A JP5962878A JP5962878A JPS54150973A JP S54150973 A JPS54150973 A JP S54150973A JP 5962878 A JP5962878 A JP 5962878A JP 5962878 A JP5962878 A JP 5962878A JP S54150973 A JPS54150973 A JP S54150973A
Authority
JP
Japan
Prior art keywords
groove
layer
metal
evaporated
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5962878A
Other languages
Japanese (ja)
Inventor
Yoshio Takagi
Masayuki Tabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5962878A priority Critical patent/JPS54150973A/en
Publication of JPS54150973A publication Critical patent/JPS54150973A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To secure easy welding to the heat sink for the semiconductor substrate and thus to enhance the heat dispersion property when the metal is evaporated on the back of the substrate by providing the groove on the back of the substrate to exhaust the residual bubbles caused at the sealing time.
CONSTITUTION: Cross-shaped groove 6 is formed through the sand blast or other methods in correspondence to each other pattern or the center of each chip onto the back of Si wafer 8 to which the upper-surface electrode through patterning. Then the solderable metal such as Ni or the like is vacuum-evaporated on the surface of the groove to form metal layer 2 and then divided into each chip 1 via the laser scriber or the like from the side of layer 2 based on the patterned pitch. Thus, escape groove 7 opposing to groove 6 is formed on the surface of layer 2 for the evaporated metal, and heat sink 4 is welded on the surface of layer 2 via solder material 3. As a result, bubble 5 left inside through the heat treatment is pushed outside along groove 7 according to the fusion expansion of material 3, thus securing the close and assured sealing.
COPYRIGHT: (C)1979,JPO&Japio
JP5962878A 1978-05-18 1978-05-18 Manufacture of semiconductor device Pending JPS54150973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5962878A JPS54150973A (en) 1978-05-18 1978-05-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5962878A JPS54150973A (en) 1978-05-18 1978-05-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54150973A true JPS54150973A (en) 1979-11-27

Family

ID=13118680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5962878A Pending JPS54150973A (en) 1978-05-18 1978-05-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54150973A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008225951A (en) * 2007-03-14 2008-09-25 Minoru Morita Korean input keyboard
JP2020136431A (en) * 2019-02-18 2020-08-31 株式会社東芝 Semiconductor device manufacturing method and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008225951A (en) * 2007-03-14 2008-09-25 Minoru Morita Korean input keyboard
JP2020136431A (en) * 2019-02-18 2020-08-31 株式会社東芝 Semiconductor device manufacturing method and semiconductor device

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