JPH1131876A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPH1131876A
JPH1131876A JP18510897A JP18510897A JPH1131876A JP H1131876 A JPH1131876 A JP H1131876A JP 18510897 A JP18510897 A JP 18510897A JP 18510897 A JP18510897 A JP 18510897A JP H1131876 A JPH1131876 A JP H1131876A
Authority
JP
Japan
Prior art keywords
circuit board
ground
semiconductor component
ground pattern
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18510897A
Other languages
Japanese (ja)
Inventor
Shinichi Miyazaki
新一 宮▲崎▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP18510897A priority Critical patent/JPH1131876A/en
Publication of JPH1131876A publication Critical patent/JPH1131876A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components

Landscapes

  • Structure Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board wherein a void or blow hole is prevented from occurring, when a semiconductor part is mounted. SOLUTION: On a rear surface of the package of a semiconductor part, a grounding layer is provided instead of a grounding lead terminal. On the front surface of a circuit board 10 where a semiconductor part is mounted, a grounding pattern 11 is formed while facing the grounding layer. A through- hole 12 is provided at a part of the grounding pattern 11 of the circuit board 10. When a semiconductor part is mounted on the circuit board 10, the grounding layer and the grounding pattern 11 are soldered. Here, the gas of flux contained in the solder and the air taken in a molten solder are evacuated via a through- hole, as well as between the grounding layer and the grounding pattern 11.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高周波で動作する
半導体部品を実装するための回路基板に関するものであ
る。
The present invention relates to a circuit board for mounting a semiconductor component operating at a high frequency.

【0002】[0002]

【従来の技術】電子機器の小型化を図るため、電子回路
を構成する電子部品の高密度化が飛躍的に進んでいる。
このため、大部分の電子部品の実装は一般に、回路基板
の表面に形成された回路パタ−ンの一部であるパッドに
電子部品の電極端子を半田付けすることによって行われ
る。
2. Description of the Related Art In order to reduce the size of electronic devices, the density of electronic components constituting electronic circuits has been dramatically increased.
For this reason, most electronic components are generally mounted by soldering the electrode terminals of the electronic component to pads that are part of a circuit pattern formed on the surface of the circuit board.

【0003】次に、実装方法の概略を説明する。まず、
回路パタ−ンが形成された回路基板の表面に、所定形状
に形成されたマスクを重ね合わせる。この後、スキ−ジ
を用いて、パットの表面に半田ペ−ストを印刷する。さ
らに、電子部品の電極端子とパッドとが重なるように電
子部品を回路基板に載置した後、リフロ−炉に流して半
田ペ−ストを溶融する。この結果、電極端子とパッドと
は、半田を介して電気的に接続される。
Next, an outline of a mounting method will be described. First,
A mask formed in a predetermined shape is superimposed on the surface of the circuit board on which the circuit pattern has been formed. Thereafter, a solder paste is printed on the surface of the pad using a squeegee. Further, after the electronic component is placed on the circuit board such that the electrode terminals of the electronic component and the pads are overlapped with each other, the electronic component is passed through a reflow furnace to melt the solder paste. As a result, the electrode terminals and the pads are electrically connected via the solder.

【0004】また、リフロ−炉を使用せずにレ−ザ−ビ
−ムを用いて半田ペ−ストを溶融する方法も知られてい
る。この方法では、特開平4−73911号公報に記載
されたように、電子部品が搭載される基板には半田ペ−
ストを溶融した際に発生する半田ペ−ストに含まれるフ
ラックスのガスや、溶融ハンダ中に取り込まれた空気を
逃がすためのガス抜き用の開口部が、電子部品の側面端
部から少なくとも一部分が露出するように設けられる。
There is also known a method of melting a solder paste using a laser beam without using a reflow furnace. In this method, as described in JP-A-4-73911, a solder paste is applied to a substrate on which electronic components are mounted.
An opening for releasing gas of flux contained in the solder paste generated when the strike is melted and air taken in the molten solder is provided at least partially from the side end of the electronic component. It is provided so as to be exposed.

【0005】さらに、近年、PHS等の移動体通信機器
やスイッチング電源等には、高周波で動作する半導体部
品が電子部品として多く使用される。一般に半導体部品
は、半導体素子と、半導体素子と電気的に接続されたリ
−ド端子とを備え、半導体素子およびリ−ド端子は樹脂
パッケ−ジされる。高周波で動作する半導体部品を用い
て電子回路を設計する場合、半導体部品のリ−ド端子が
インダクタンス成分として働くため、リ−ド端子の数が
少ないほうが望ましい。従って、高周波で動作する半導
体部品では、接地用のリ−ド端子を省いてリ−ド端子の
数を減らした製品が開発されている。
In recent years, semiconductor components operating at a high frequency are often used as electronic components in mobile communication devices such as PHS, switching power supplies, and the like. Generally, a semiconductor component has a semiconductor element and a lead terminal electrically connected to the semiconductor element, and the semiconductor element and the lead terminal are packaged with a resin. When designing an electronic circuit using a semiconductor component that operates at a high frequency, the number of the lead terminals is desirably small because the lead terminal of the semiconductor component functions as an inductance component. Accordingly, for semiconductor components operating at high frequencies, products have been developed in which the number of lead terminals is reduced by eliminating the ground lead terminals.

【0006】図5に示すように、接地用のリ−ド端子を
省いた高周波で動作する半導体部品1では、接地用のリ
−ド端子の代わりに、例えば金メッキ等による接地層2
が半導体部品1の樹脂あるいはセラミック等のパッケ−
ジの底面に形成され、半導体部品1を構成する半導体素
子(図示せず)の接地端子と接地層2とが電気的に直接
接続される。
As shown in FIG. 5, in a semiconductor component 1 which operates at a high frequency without a ground lead terminal, a ground layer 2 made of, for example, gold plating is used instead of the ground lead terminal.
Is a package of resin or ceramic of the semiconductor component 1
A ground terminal of a semiconductor element (not shown) forming the semiconductor component 1 and a ground layer 2 is formed on the bottom surface of the semiconductor device, and is electrically connected directly.

【0007】そして、半導体部品1を回路基板3に実装
する場合は、接地層2と対向する回路基板3の表面に接
地パタ−ン4が形成され、接地層2と接地パタ−ン4と
が半田5を介して電気的に接続される。半導体部品1の
接地用以外のリ−ド端子6は、回路基板3の表面に形成
された回路パタ−ンの一部であるパッド7に半田5を介
して電気的に接続される。
When the semiconductor component 1 is mounted on the circuit board 3, a ground pattern 4 is formed on the surface of the circuit board 3 facing the ground layer 2, and the ground layer 2 and the ground pattern 4 are connected to each other. They are electrically connected via the solder 5. A lead terminal 6 other than the ground terminal of the semiconductor component 1 is electrically connected via a solder 5 to a pad 7 which is a part of a circuit pattern formed on the surface of the circuit board 3.

【0008】また、半田5を介して接地層2と接地パタ
−ン4が接続されるので、半導体部品1を構成する半導
体素子で発生した熱は、接地層2および半田5を介して
接地パタ−ン4に効率良く逃げる。このため、半導体部
品1を用いて設計した電子回路の温度上昇が低減され、
温度上昇に伴う誤動作等を防ぐことができる。
Further, since the grounding layer 2 and the grounding pattern 4 are connected via the solder 5, heat generated in the semiconductor element constituting the semiconductor component 1 is not affected by the grounding pattern via the grounding layer 2 and the soldering 5. -Efficient escape to 4 For this reason, the temperature rise of the electronic circuit designed using the semiconductor component 1 is reduced,
Malfunction due to temperature rise can be prevented.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、半導体
部品1を回路基板3に実装する際、半田ペ−ストを溶融
させるために加えられる熱が接地パタ−ン4に逃げやす
く、接地層2および接地パタ−ン4の近傍温度が均一に
上昇しないという問題がある。この結果、半田ペ−スト
が溶融されにくくなり、リフロ−炉の温度を比較的高め
に設定しなければならなかった。
However, when the semiconductor component 1 is mounted on the circuit board 3, the heat applied to melt the solder paste can easily escape to the ground pattern 4, so that the ground layer 2 and the ground can be removed. There is a problem that the temperature near the pattern 4 does not rise uniformly. As a result, the solder paste is hardly melted, and the temperature of the reflow furnace must be set relatively high.

【0010】一方、半導体部品1を高い温度中に長時間
保持すると、半導体部品1を構成する半導体素子のジャ
ンクション部分の耐熱性から半導体素子が熱破壊してし
まう。従って、リフロ−炉に保持する時間をできるだけ
短かくしなければならなかった。この結果、半田ペ−ス
トを溶融した際に発生する半田ペ−ストに含まれるフラ
ックスのガスや、溶融ハンダ中に取り込まれた空気が、
接地層2と接地パタ−ン4との間から充分に逃げ切ら
ず、ボイド8やブロ−ホ−ル9の発生原因となってい
た。このため、半導体部品1の位置ズレや、傾きが発生
するという問題があった。また、接地層2と接地パタ−
ン4との間の接着面積が減少するため、高周波の接地特
性や、放熱効果の低下という問題や、さらに、ヒ−トサ
イクルが加わるような状態で使用する場合には接続強度
の低下が著しく電気的信頼性に欠けるという問題もあっ
た。
On the other hand, if the semiconductor component 1 is held at a high temperature for a long time, the semiconductor element will be thermally damaged due to the heat resistance of the junction of the semiconductor element constituting the semiconductor component 1. Therefore, the time required for holding in the reflow furnace had to be as short as possible. As a result, the flux gas contained in the solder paste generated when the solder paste is melted, and the air taken into the molten solder,
The space between the grounding layer 2 and the grounding pattern 4 did not escape sufficiently, causing voids 8 and blowholes 9 to be generated. For this reason, there has been a problem that the position shift and the inclination of the semiconductor component 1 occur. Also, the ground layer 2 and the ground pattern
In this case, the bonding area with the heat sink 4 is reduced, so that the high frequency grounding characteristics and the heat radiation effect are deteriorated. Further, when the heat cycle is used, the connection strength is significantly reduced. There was also a problem of lack of electrical reliability.

【0011】そこで、本発明は上記問題を解決するため
高周波で動作をする半導体部品を実装するための回路基
板を提供することを目的とする。
Accordingly, an object of the present invention is to provide a circuit board for mounting a semiconductor component operating at a high frequency to solve the above problem.

【0012】[0012]

【課題を解決するための手段】本発明は、上記目的を達
成するために次のように構成される。すなわち、第一
に、半導体部品を実装する回路基板において、前記半導
体部品の底面に設けられた接地層と対向する位置に形成
されて該接地層と半田付けされる接地パタ−ンを有し、
該接地パタ−ン部分には貫通孔が形成されているもので
ある。
The present invention is configured as follows to achieve the above object. That is, first, the circuit board on which the semiconductor component is mounted has a ground pattern formed at a position facing the ground layer provided on the bottom surface of the semiconductor component and soldered to the ground layer,
A through hole is formed in the ground pattern.

【0013】半田付する際に、接地層と接地パタ−ンの
間に発生する、半田ペ−ストに含まれるフラックスのガ
スや、溶融半田中に取り込まれた空気が、貫通孔を介し
て気散する。
During the soldering, the gas of the flux contained in the solder paste and the air taken in the molten solder generated between the ground layer and the ground pattern pass through the through holes. Scatter.

【0014】第二に、半導体部品を実装する回路基板に
おいて、前記半導体部品の底面に設けられた接地層と対
向する位置に形成され且つ前記接地層と半田付けされる
接地パタ−ンを有し、該接地パタ−ン部分には少なくと
も一方の端部を接地パタ−ンの周縁として絶縁基板を露
出させる溝が形成されているものである。
Second, the circuit board on which the semiconductor component is mounted has a ground pattern formed at a position facing the ground layer provided on the bottom surface of the semiconductor component and soldered to the ground layer. A groove for exposing the insulating substrate is formed in the ground pattern portion, at least one end of which is a peripheral edge of the ground pattern.

【0015】半田付する際に、接地層と接地パタ−ンの
間に発生する、半田ペ−ストに含まれるフラックスのガ
スや、溶融半田中に取り込まれた空気が、溝を介して気
散する。
During soldering, the flux gas contained in the solder paste and the air taken into the molten solder generated between the ground layer and the ground pattern are diffused through the grooves. I do.

【0016】[0016]

【発明の実施の形態】図1および図2を用いて、請求項
1に係る回路基板10について説明する。なお、従来と
同じ構成部分は同じ番号を用いて説明する。また、回路
基板10は、高周波で動作する半導体部品1を実装する
部分についてのみ説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit board 10 according to claim 1 will be described with reference to FIGS. Note that the same components as those in the related art will be described using the same numbers. In addition, only the portion of the circuit board 10 on which the semiconductor component 1 operating at a high frequency is mounted will be described.

【0017】図1のように、半導体部品1を実装する回
路基板10の表面には、回路パタ−ンの一部であるパッ
ド7と、接地パタ−ン11が設けられる。パッド7は、
半導体部品1を回路基板10に実装した際に、半導体部
品1を構成する半導体素子(図示せず)に接続されたリ
−ド端子6と電気的に接続される。また、接地パタ−ン
11は、半導体部品1の樹脂パッケ−ジの底面に設けら
れた接地層2と対向するように形成される。一般に、接
地パタ−ン11は、回路基板10の形状を小形にするた
め、接地層2とほぼ大きさの同じ形状に形成される。な
お、接地パタ−ン11を接地層2よりも大きく形成した
場合は、半導体部品1の放熱効果がより大きくなる。
As shown in FIG. 1, a pad 7 which is a part of a circuit pattern and a ground pattern 11 are provided on the surface of a circuit board 10 on which the semiconductor component 1 is mounted. Pad 7
When the semiconductor component 1 is mounted on the circuit board 10, it is electrically connected to a lead terminal 6 connected to a semiconductor element (not shown) constituting the semiconductor component 1. The ground pattern 11 is formed so as to face the ground layer 2 provided on the bottom surface of the resin package of the semiconductor component 1. Generally, the ground pattern 11 is formed in the same shape as the ground layer 2 so as to make the circuit board 10 small. When the ground pattern 11 is formed larger than the ground layer 2, the heat radiation effect of the semiconductor component 1 is increased.

【0018】さらに、回路基板10の接地パタ−ン11
の部分には、少なくとも一以上の貫通孔12が形成され
る。貫通孔12は、ガス抜きの役目を果たすために設け
られる。このため、貫通孔12の開口は、溶融した半田
の毛細管減少によって塞がれない程度の大きさに形成さ
れる。貫通孔12は、一般にドリルを用いて形成され
る。従って、貫通孔12の内径は、スル−ホ−ルに用い
られる300μm程度の大きさに通常は形成される。ま
た、貫通孔12は、接地層2および接地パタ−ン11の
形状を考慮して、フラックスのガスや、溶融半田中に取
り込まれた空気が気散しにくい、例えば接地パタ−ン1
1の中央部に形成される。貫通孔12の数は、接地パタ
−ン11の大きさ、あるいは形状を考慮して適宜選択さ
れる。
Further, a ground pattern 11 of the circuit board 10 is provided.
, At least one or more through-holes 12 are formed. The through-hole 12 is provided to fulfill the function of degassing. For this reason, the opening of the through hole 12 is formed in such a size that it is not blocked by the decrease in the capillary of the molten solder. The through holes 12 are generally formed using a drill. Therefore, the inner diameter of the through hole 12 is usually formed to a size of about 300 μm used for a through hole. In addition, the through holes 12 are formed by considering the shapes of the ground layer 2 and the ground pattern 11 so that the gas of the flux and the air taken into the molten solder are not easily diffused.
1 is formed at the center. The number of the through holes 12 is appropriately selected in consideration of the size or shape of the ground pattern 11.

【0019】次に、実装方法の概略を説明する。まず、
回路パタ−ンが形成された回路基板10の表面に、所定
形状に形成されたマスクを重ね合わせる。この後、スキ
−ジを用いて、パット7および接地パタ−ン11の表面
に半田ペ−ストを印刷する。さらに、半導体部品1のリ
−ド端子6とパッド7が重なるように、半導体部品1を
回路基板10に載置する。このとき、接地層2と接地パ
タ−ン11とは重なる。この後、半導体部品1を載置し
た回路基板10をリフロ−炉に流して、半田ペ−ストを
溶融する。なお、半田ペ−ストを溶融させるために加え
られる熱は接地パタ−ン11に逃げやすいため、パッド
7に比べて接地パタ−ン11の温度上昇が遅くなる。こ
のため、接地層2の代わりに接地用のリ−ド端子が設け
られた高周波で動作する半導体部品を実装する場合に比
べて、リフロ−炉の温度は高めに設定されるとともに、
リフロ−炉に保持する時間は短かく設定される。
Next, an outline of the mounting method will be described. First,
A mask formed in a predetermined shape is superimposed on the surface of the circuit board 10 on which the circuit pattern has been formed. Thereafter, a solder paste is printed on the surfaces of the pad 7 and the ground pattern 11 using a squeegee. Further, the semiconductor component 1 is mounted on the circuit board 10 so that the lead terminals 6 and the pads 7 of the semiconductor component 1 overlap. At this time, the ground layer 2 and the ground pattern 11 overlap. Thereafter, the circuit board 10 on which the semiconductor component 1 is mounted is passed through a reflow furnace to melt the solder paste. Since the heat applied to melt the solder paste easily escapes to the ground pattern 11, the temperature rise of the ground pattern 11 is slower than that of the pad 7. For this reason, the temperature of the reflow furnace is set higher than in the case where a semiconductor component operating at a high frequency provided with a grounding lead terminal instead of the grounding layer 2 is mounted.
The holding time in the reflow furnace is set short.

【0020】このとき、接地層2と接地パタ−ン11の
間に発生するフラックスのガスや、溶融ハンダ中に取り
込まれた空気は、接地層2と接地パタ−ン11の間から
だけではなく、貫通孔12を気道として気散される。こ
の結果、接地層2と接地パタ−ン11の間には、ボイド
8やブロ−ホ−ル9の発生が防止される。
At this time, the gas of the flux generated between the ground layer 2 and the ground pattern 11 and the air taken into the molten solder are not limited to the space between the ground layer 2 and the ground pattern 11. The air is diffused using the through holes 12 as airways. As a result, between the ground layer 2 and the ground pattern 11, the occurrence of the void 8 and the blow hole 9 is prevented.

【0021】上述した回路基板10では、回路基板10
における接地パタ−ン11の部分に貫通孔12を形成し
たが、これに限られることはない。図3を用いて、請求
項2に係る第一の回路基板13について説明する。
In the circuit board 10 described above, the circuit board 10
Although the through hole 12 is formed in the portion of the ground pattern 11 in the above, the present invention is not limited to this. The first circuit board 13 according to claim 2 will be described with reference to FIG.

【0022】回路基板13の表面には、回路パタ−ンの
一部であるパッド7と、接地パタ−ン14が設けられ
る。
On the surface of the circuit board 13, a pad 7 which is a part of a circuit pattern and a ground pattern 14 are provided.

【0023】回路基板13の接地パタ−ン14の部分に
は、少なくとも一以上の溝15が形成される。溝15は
接地パタ−ン14の周縁から接地パタ−ン14の中央付
近に伸びるように形成される。溝15の内壁に溶融した
半田が付着すると溝15が塞がれてしまうので、溝15
はフラックスのガスや、溶融半田中に取り込まれた空気
を、気散させるための気道として機能しなくなる。この
ため、溝15は、接地パタ−ン14の下層の回路基板1
3を構成する絶縁基板16の表面を露出するように形成
される。なお、絶縁基板16は、例えばガラス繊維にエ
ポキシ樹脂を含浸して形成された基板や、セラミック基
板で形成されるので溶融半田は付着せず、溝15は塞が
れない。
At least one groove 15 is formed in the ground pattern 14 of the circuit board 13. The groove 15 is formed so as to extend from the periphery of the ground pattern 14 to the vicinity of the center of the ground pattern 14. If the molten solder adheres to the inner wall of the groove 15, the groove 15 will be closed.
Does not function as an airway for diffusing the gas of the flux or the air taken into the molten solder. For this reason, the groove 15 is formed in the circuit board 1 below the ground pattern 14.
3 is formed so as to expose the surface of the insulating substrate 16. Since the insulating substrate 16 is formed of, for example, a substrate formed by impregnating glass fiber with an epoxy resin or a ceramic substrate, molten solder does not adhere thereto, and the groove 15 is not closed.

【0024】また、溝15は、パタ−ンエッチング等に
よる化学的方法を用いて、溝15の幅が300μm程度
となるように形成される。また、溝15は、接地パタ−
ン14の形状を考慮して、フラックスのガスや、溶融半
田中に取り込まれた空気が気散しにくい部分に形成され
る。
The groove 15 is formed by a chemical method such as pattern etching so that the width of the groove 15 is about 300 μm. The groove 15 is provided with a ground pattern.
In consideration of the shape of the solder 14, the flux gas and the air taken into the molten solder are formed in a portion where it is difficult to diffuse.

【0025】さらに、溝15の数は、接地パタ−ン14
の大きさ、あるいは形状により適宜選択される。溝15
が複数形成される場合は、溝15を放射状に形成しても
良いし、平行に形成しても良いし、交差するように形成
しても良い。また、溝15は、接地パタ−ン14を分割
するように形成しても良い。なお、溝15によって接地
パタ−ン14が複数に分割された場合は、分割された接
地パタ−ン14のそれぞれの部分を接地した場合に、半
導体部品1で発生した熱を効率良く逃がすことができ
る。
Further, the number of grooves 15 depends on the ground pattern 14.
Is appropriately selected depending on the size or the shape of. Groove 15
When a plurality of grooves 15 are formed, the grooves 15 may be formed radially, may be formed in parallel, or may be formed to intersect. Further, the groove 15 may be formed so as to divide the ground pattern 14. In the case where the ground pattern 14 is divided into a plurality of parts by the groove 15, when each part of the divided ground pattern 14 is grounded, it is possible to efficiently release the heat generated in the semiconductor component 1. it can.

【0026】なお、溝15は、化学的方法を用いて形成
する代わりに、エンドミルを用いて切削する等の物理的
方法によって形成しても良い。図4を用いて、請求項2
に係る第二の回路基板17について説明する。
The grooves 15 may be formed by a physical method such as cutting using an end mill instead of using a chemical method. Referring to FIG.
The second circuit board 17 according to the above will be described.

【0027】回路基板17は、接地パタ−ン18の部分
にエンドミルを用いて切削して形成した溝19を有す
る。
The circuit board 17 has a groove 19 formed by cutting using an end mill in the ground pattern 18.

【0028】エンドミルを用いて接地パタ−ン18を切
削する場合は、接地パタ−ン18だけでなく、絶縁基板
16の表面層も除去する。このため、溝19の底面は絶
縁基板16の表面よりも低くなり、溝19の深さは化学
的方法によって形成された溝15よりも深くなる。この
ため溝19の断面形状は、溝の幅が同じならば、化学的
方法を用いて形成した溝15に比べて大きくなり、フラ
ックスのガスや、溶融半田中に取り込まれた空気を気散
させる気道としての効果は大きくなる。
When cutting the ground pattern 18 using an end mill, not only the ground pattern 18 but also the surface layer of the insulating substrate 16 is removed. For this reason, the bottom surface of the groove 19 is lower than the surface of the insulating substrate 16, and the depth of the groove 19 is deeper than the groove 15 formed by a chemical method. Therefore, if the width of the groove 19 is the same, the cross-sectional shape of the groove 19 becomes larger than that of the groove 15 formed by using a chemical method, and the gas of the flux and the air taken in the molten solder are diffused. The effect as an airway increases.

【0029】[0029]

【発明の効果】本発明は、上述のような構成であるから
次のような効果を有する。すなわち、接地層と接地パタ
−ンの間に発生するフラックスのガスや、溶融ハンダ中
に取り込まれた空気は、接地層と接地パタ−ンの間から
だけではなく、貫通孔あるいは溝を介しても気散され
る。この結果、接地層と接地パタ−ンの間には、ボイド
やブロ−ホ−ルの発生が防止される。このため、半導体
部品の位置ズレや、傾きが発生しにくくなる。従って、
高周波で動作をする半導体部品を回路基板に実装する際
の歩留まりが向上する。また、半導体部品の接地層と接
地パタ−ンとの間の接着面積が一定となるので、半導体
部品の高周波特性のバラツキが減少するとともに、放熱
効果の低下を防ぐことができる。さらに、ヒ−トサイク
ルが加わるような状態で実装した回路基板を使用する場
合でも、接続強度の著しく低下を防ぐことができ、電気
的信頼性が向上する。
The present invention has the following effects because it has the above-described configuration. That is, the gas of the flux generated between the ground layer and the ground pattern and the air taken into the molten solder not only come from between the ground layer and the ground pattern but also through the through holes or grooves. Is also distracted. As a result, generation of voids and blowholes between the ground layer and the ground pattern is prevented. For this reason, misalignment and inclination of the semiconductor component are less likely to occur. Therefore,
The yield when mounting a semiconductor component operating at a high frequency on a circuit board is improved. Further, since the bonding area between the ground layer and the ground pattern of the semiconductor component becomes constant, the variation in the high-frequency characteristics of the semiconductor component is reduced, and the reduction of the heat radiation effect can be prevented. Further, even when a circuit board mounted in a state where a heat cycle is applied is used, a remarkable decrease in connection strength can be prevented, and electrical reliability is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】請求項1の回路基板であり、図1(a)は上面
図の一部であり、図1(b)は図1(a)におけるA−
A´での断面図である。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit board according to claim 1, FIG. 1A is a part of a top view, and FIG.
It is sectional drawing in A '.

【図2】請求項1の回路基板に半導体部品を実装した図
であり、図2(a)は上面図の一部であり、図2(b)
は図2(a)におけるA−A´での断面図である。
FIG. 2A is a diagram showing a semiconductor component mounted on the circuit board according to claim 1; FIG. 2A is a part of a top view, and FIG.
FIG. 2 is a cross-sectional view taken along line AA ′ in FIG.

【図3】請求項2の回路基板であり、図3(a)は上面
図の一部であり、図3(b)は図3(a)におけるA−
A´での断面図である。
3 (a) is a part of a top view, and FIG. 3 (b) is a circuit board of FIG. 3 (a); FIG.
It is sectional drawing in A '.

【図4】請求項2の回路基板であり、図4(a)は上面
図の一部であり、図4(b)は図4(a)におけるA−
A´での断面図である。
4 (a) is a part of a top view, and FIG. 4 (b) is a circuit board of FIG. 4 (a);
It is sectional drawing in A '.

【図5】従来の回路基板に半導体部品を実装した図であ
り、図5(a)は上面図の一部であり、図5(b)は図
5(a)におけるA−A´での断面図である。
5A and 5B are diagrams in which semiconductor components are mounted on a conventional circuit board, FIG. 5A is a part of a top view, and FIG. 5B is a view taken along a line AA ′ in FIG. It is sectional drawing.

【符号の説明】[Explanation of symbols]

10 回路基板 11 接地パタ−ン 12 貫通孔 Reference Signs List 10 circuit board 11 ground pattern 12 through hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体部品を実装する回路基板におい
て、前記半導体部品の底面に設けられた接地層と対向す
る位置に形成されて該接地層と半田付けされる接地パタ
−ンを有し、該接地パタ−ン部分には貫通孔が形成され
ていることを特徴とする回路基板。
A circuit board on which a semiconductor component is mounted, the circuit board having a ground pattern formed at a position facing a ground layer provided on a bottom surface of the semiconductor component and soldered to the ground layer; A circuit board, wherein a through hole is formed in a ground pattern portion.
【請求項2】 半導体部品を実装する回路基板におい
て、前記半導体部品の底面に設けられた接地層と対向す
る位置に形成され且つ前記接地層と半田付けされる接地
パタ−ンを有し、該接地パタ−ン部分には少なくとも一
方の端部を接地パタ−ンの周縁として絶縁基板を露出さ
せる溝が形成されていることを特徴とする回路基板。
2. A circuit board on which a semiconductor component is mounted, the circuit board having a ground pattern formed at a position facing a ground layer provided on a bottom surface of the semiconductor component and soldered to the ground layer. A circuit board, wherein a groove for exposing an insulating substrate is formed in at least one end portion of the ground pattern portion as a peripheral edge of the ground pattern.
JP18510897A 1997-07-10 1997-07-10 Circuit board Pending JPH1131876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18510897A JPH1131876A (en) 1997-07-10 1997-07-10 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18510897A JPH1131876A (en) 1997-07-10 1997-07-10 Circuit board

Publications (1)

Publication Number Publication Date
JPH1131876A true JPH1131876A (en) 1999-02-02

Family

ID=16165005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18510897A Pending JPH1131876A (en) 1997-07-10 1997-07-10 Circuit board

Country Status (1)

Country Link
JP (1) JPH1131876A (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003028414A1 (en) * 2001-09-28 2003-04-03 Intel Corporation Vented vias for via in pad technology assembly process yield improvements
JP2006351926A (en) * 2005-06-17 2006-12-28 Auto Network Gijutsu Kenkyusho:Kk Circuit board, electronic component, and electric connection box
JP2008135691A (en) * 2006-10-30 2008-06-12 Denso Corp Wiring board
JP2010016129A (en) * 2008-07-02 2010-01-21 Fujitsu Ten Ltd Printed circuit board and radar apparatus
JP2010171441A (en) * 2010-03-17 2010-08-05 Renesas Electronics Corp Electronic circuit board
JP2012222110A (en) * 2011-04-07 2012-11-12 Mitsubishi Electric Corp Printed wiring board and printed circuit board
WO2013005720A1 (en) * 2011-07-06 2013-01-10 株式会社 豊田自動織機 Circuit board, and manufacturing method for circuit board
JP2013084960A (en) * 2011-10-11 2013-05-09 Led Engin Inc Grooved plate for solder joint
WO2013136575A1 (en) * 2012-03-15 2013-09-19 株式会社日立製作所 Printed wiring board and circuit board
EP2688095A2 (en) 2012-07-18 2014-01-22 Nichia Corporation Semiconductor component support and semiconductor device
JP2014078766A (en) * 2014-02-05 2014-05-01 Toyota Industries Corp Circuit board and manufacturing method therefor
JP2016127207A (en) * 2015-01-07 2016-07-11 三菱電機株式会社 Mounting board and manufacturing method for the same, and printed wiring plate and electronic component
WO2016127897A1 (en) * 2015-02-15 2016-08-18 华为技术有限公司 Power tube connecting structure of power amplifier and power amplifier
JP2016184756A (en) * 2016-06-10 2016-10-20 日亜化学工業株式会社 Semiconductor element mounting member and semiconductor device
JP2017162994A (en) * 2016-03-09 2017-09-14 パナソニックIpマネジメント株式会社 Mounting structure of heating component and manufacturing method thereof
JP2017195298A (en) * 2016-04-21 2017-10-26 三菱電機株式会社 Electronic component device and method of manufacturing the same
JP2018006654A (en) * 2016-07-06 2018-01-11 株式会社デンソー Electronic device

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100433949C (en) * 2001-09-28 2008-11-12 英特尔公司 Vented vias for via in pad technology assembly process yield improvements
WO2003028414A1 (en) * 2001-09-28 2003-04-03 Intel Corporation Vented vias for via in pad technology assembly process yield improvements
JP4634230B2 (en) * 2005-06-17 2011-02-16 株式会社オートネットワーク技術研究所 Circuit boards, electronic components and electrical junction boxes
JP2006351926A (en) * 2005-06-17 2006-12-28 Auto Network Gijutsu Kenkyusho:Kk Circuit board, electronic component, and electric connection box
JP2008135691A (en) * 2006-10-30 2008-06-12 Denso Corp Wiring board
JP2010016129A (en) * 2008-07-02 2010-01-21 Fujitsu Ten Ltd Printed circuit board and radar apparatus
JP2010171441A (en) * 2010-03-17 2010-08-05 Renesas Electronics Corp Electronic circuit board
JP2012222110A (en) * 2011-04-07 2012-11-12 Mitsubishi Electric Corp Printed wiring board and printed circuit board
CN103621190A (en) * 2011-07-06 2014-03-05 株式会社丰田自动织机 Circuit board, and manufacturing method for circuit board
WO2013005720A1 (en) * 2011-07-06 2013-01-10 株式会社 豊田自動織機 Circuit board, and manufacturing method for circuit board
JP2013016741A (en) * 2011-07-06 2013-01-24 Toyota Industries Corp Circuit board and manufacturing method therefor
TWI448219B (en) * 2011-07-06 2014-08-01 豐田自動織機股份有限公司 Circuit board and method for manufacturing the same
JP2013084960A (en) * 2011-10-11 2013-05-09 Led Engin Inc Grooved plate for solder joint
WO2013136575A1 (en) * 2012-03-15 2013-09-19 株式会社日立製作所 Printed wiring board and circuit board
EP2688095A2 (en) 2012-07-18 2014-01-22 Nichia Corporation Semiconductor component support and semiconductor device
JP2014022576A (en) * 2012-07-18 2014-02-03 Nichia Chem Ind Ltd Semiconductor element mounting member and semiconductor device
US10068821B2 (en) 2012-07-18 2018-09-04 Nichia Corporation Semiconductor component support and semiconductor device
JP2014078766A (en) * 2014-02-05 2014-05-01 Toyota Industries Corp Circuit board and manufacturing method therefor
JP2016127207A (en) * 2015-01-07 2016-07-11 三菱電機株式会社 Mounting board and manufacturing method for the same, and printed wiring plate and electronic component
WO2016127897A1 (en) * 2015-02-15 2016-08-18 华为技术有限公司 Power tube connecting structure of power amplifier and power amplifier
JP2018506860A (en) * 2015-02-15 2018-03-08 華為技術有限公司Huawei Technologies Co.,Ltd. Power pipe connection structure for power amplifier and power amplifier
US10165687B2 (en) 2015-02-15 2018-12-25 Huawei Technologies Co., Ltd. Power tube connection structure of power amplifier and power amplifier
US10426036B2 (en) 2015-02-15 2019-09-24 Huawei Technologies Co., Ltd. Power tube connection structure of power amplifier and power amplifier
JP2017162994A (en) * 2016-03-09 2017-09-14 パナソニックIpマネジメント株式会社 Mounting structure of heating component and manufacturing method thereof
JP2017195298A (en) * 2016-04-21 2017-10-26 三菱電機株式会社 Electronic component device and method of manufacturing the same
JP2016184756A (en) * 2016-06-10 2016-10-20 日亜化学工業株式会社 Semiconductor element mounting member and semiconductor device
JP2018006654A (en) * 2016-07-06 2018-01-11 株式会社デンソー Electronic device

Similar Documents

Publication Publication Date Title
JPH1131876A (en) Circuit board
JP3639505B2 (en) Printed wiring board and semiconductor device
JP2004063864A (en) Printed circuit board and soldered structure of electronic component
US6399417B1 (en) Method of fabricating plated circuit lines over ball grid array substrate
KR20010078779A (en) Semiconductor device using a BGA package and method of producing the same
KR101019642B1 (en) Method of Manufacturing Print Circuit Board
EP1377144A2 (en) Method of mounting a leadless package and structure therefor
JPH07288375A (en) Circuit board
JPH0368157A (en) High frequency thick film integrated circuit device
JP2001358442A (en) Mount structure of semiconductor package
JP2002368027A (en) Method of manufacturing semiconductor device
JP2010251354A (en) Electronic circuit board
JP2012222110A (en) Printed wiring board and printed circuit board
JPH05315778A (en) Electronic parts mounting board provided with heat sink
JPH098444A (en) Electronic circuit device
JPH04279097A (en) Heat dissipating structure for printed wiring board
JPH1187907A (en) Soldering mounting method for mounting component
JPH0595071A (en) Substrate for mounting electronic component and manufacture thereof
JPH1051094A (en) Printed wiring board, and its manufacture
US6560121B1 (en) Method for surface mounting of a microwave package on a printed circuit and package and printed circuit for implementing said method
JP3258564B2 (en) Semiconductor device and manufacturing method thereof
JP2023092556A (en) Print circuit board
JP2006005112A (en) Semiconductor device and circuit board used therefor
JPH10112514A (en) Semiconductor device and its manufacture
JPH06112275A (en) Manufacture of circuit wiring board provided with terminal for mounting circuit component

Legal Events

Date Code Title Description
A977 Report on retrieval

Effective date: 20051128

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20051220

A02 Decision of refusal

Effective date: 20060509

Free format text: JAPANESE INTERMEDIATE CODE: A02