JP2006344477A - Chip type fuse - Google Patents

Chip type fuse Download PDF

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JP2006344477A
JP2006344477A JP2005168517A JP2005168517A JP2006344477A JP 2006344477 A JP2006344477 A JP 2006344477A JP 2005168517 A JP2005168517 A JP 2005168517A JP 2005168517 A JP2005168517 A JP 2005168517A JP 2006344477 A JP2006344477 A JP 2006344477A
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metal layer
layer
fuse
chip
barrier metal
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JP4632358B2 (en
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Hitoshi Inaba
均 稲場
Katsuya Yamagishi
克哉 山岸
Tatsuki Hirano
立樹 平野
Hitoshi Sato
仁 佐藤
Hideki Kiyono
英樹 清野
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Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip type fuse with more stable fusion characteristics and an improved yield. <P>SOLUTION: The chip type fuse is provided an insulating substrate 1, a pair of end-face electrodes formed at either end part of the insulating substrate 1, and a metal fuse part 4 formed on a top face of the insulating substrate 1 with either end connected to the pair of end-face electrodes 2. The fuse part 4 is provided with a Cu layer 5a with its either end connected to the pair of end-face electrodes 2, and a second element layer 6 formed on a given intermediate part of the Cu layer 5a through a barrier metal layer 5b and a metal with a lower melting point than the barrier metal layer 5b, and the barrier metal layer 5b is formed in an area wider than a formation area of the second element 6. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、過電流による回路破壊を防止するため各種電子機器に使用されるチップ型ヒューズに関する。   The present invention relates to a chip-type fuse used in various electronic devices in order to prevent circuit breakdown due to overcurrent.

電子機器に故障等で生じた過電流の流入により回路破壊が発生することを防止するためにヒューズが用いられているが、近年、装置の小型化に伴って配線板等に表面実装が容易で量産性に優れたチップ型ヒューズが採用されるようになってきた。
従来、例えば特許文献１には、ヒューズ膜の溶断部下にシリコーン系樹脂が充填されていると共に、ヒューズ膜をエポキシ系樹脂の保護膜で覆ったチップヒューズが提案されている。このチップヒューズでは、図６に示すように、Ｃｕ（銅）箔のヒューズ膜であるＣｕ層１００上にＳｎ（錫）膜１０１を形成し、Ｃｕ層１００へのＳｎの拡散を防止するために、Ｓｎ膜１０１形成前に、Ｃｕ層１００上にバリア層としてＮｉ（ニッケル）膜１０２をＳｎ膜１０１と同じ形成領域にパターン形成することで、溶断特性の調整を行う技術が記載されている。 Fuse is used to prevent circuit breakdown due to inflow of overcurrent caused by failure in electronic equipment, but in recent years, surface mounting on wiring boards etc. has become easier with downsizing of devices. Chip-type fuses with excellent mass productivity have been adopted.
Conventionally, for example, Patent Document 1 proposes a chip fuse in which a silicone resin is filled under a fusing portion of a fuse film and the fuse film is covered with a protective film of an epoxy resin. In this chip fuse, as shown in FIG. 6, an Sn (tin) film 101 is formed on a Cu layer 100 that is a fuse film of Cu (copper) foil to prevent the diffusion of Sn into the Cu layer 100. A technique is described in which the fusing characteristics are adjusted by forming a Ni (nickel) film 102 as a barrier layer on the Cu layer 100 in the same formation region as the Sn film 101 before the Sn film 101 is formed.

特開２００４−３１９１６８号公報（段落番号００１０、図１）Japanese Patent Laying-Open No. 2004-319168 (paragraph number 0010, FIG. 1)

上記従来の技術には、以下の課題が残されている。
すなわち、上記特許文献１では、ヒューズ膜であるＣｕ層上に、Ｓｎ膜の形成領域と同じ領域にバリア層としてＮｉ膜をパターン形成しているが、バリア層であるＮｉ層が液状化する前にＳｎ膜が液状化した場合、ＳｎがＮｉ膜の端の部分からＣｕ層上に流れ出るおそれがあり、直接ＳｎがＣｕ層に接触してヒューズ毎に溶断時間等の溶断特性がばらつく不都合があった。 The following problems remain in the conventional technology.
That is, in Patent Document 1, a Ni film is patterned as a barrier layer in the same region as the Sn film formation region on the Cu layer that is a fuse film, but before the Ni layer that is a barrier layer is liquefied. In addition, when the Sn film is liquefied, Sn may flow out from the end portion of the Ni film onto the Cu layer, and there is a disadvantage that the fusing characteristics such as fusing time vary for each fuse because Sn directly contacts the Cu layer. It was.

本発明は、前述の課題に鑑みてなされたもので、より溶断特性が安定し、歩留まりが向上するチップ型ヒューズを提供することを目的とする。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a chip-type fuse with more stable fusing characteristics and improved yield.

本発明は、前記課題を解決するために以下の構成を採用した。すなわち、本発明のチップ型ヒューズは、絶縁基板と、前記絶縁基板の両端部に形成された一対の電極と、前記絶縁基板の上面に形成され前記一対の電極に両端が接続された金属のヒューズ部と、を備え、前記ヒューズ部が、前記一対の電極に両端が接続された第１金属層と、前記第１金属層の所定の中間部分にバリア金属層を介して積層され前記第１金属層及び前記バリア金属層よりも低融点な金属で形成された第２金属層と、を備え、前記バリア金属層が、前記第２金属層の形成領域よりも広い領域で形成されていることを特徴とする。   The present invention employs the following configuration in order to solve the above problems. That is, the chip-type fuse of the present invention includes an insulating substrate, a pair of electrodes formed at both ends of the insulating substrate, and a metal fuse formed on the upper surface of the insulating substrate and connected at both ends to the pair of electrodes. A first metal layer having both ends connected to the pair of electrodes, and a first metal layer laminated on a predetermined intermediate portion of the first metal layer via a barrier metal layer. And a second metal layer formed of a metal having a melting point lower than that of the barrier metal layer, and the barrier metal layer is formed in a region wider than a region where the second metal layer is formed. Features.

このチップ型ヒューズでは、バリア金属層が、第２金属層の形成領域よりも広い領域で形成されているので、第２金属層が液状化して形成領域から流れ出ても第１金属層に直接接触することを抑制することができる。   In this chip type fuse, since the barrier metal layer is formed in a region wider than the formation region of the second metal layer, even if the second metal layer liquefies and flows out of the formation region, it directly contacts the first metal layer. Can be suppressed.

また、本発明のチップ型ヒューズは、前記バリア金属層が、前記第１金属層の全体を覆って形成されていることを特徴とする。すなわち、このチップ型ヒューズでは、バリア金属層が第１金属層の全体を覆って形成されているので、第２金属層が液状化して形成領域から大幅に流れ出ても第１金属層に直接接触することを防ぐことができる。   The chip-type fuse of the present invention is characterized in that the barrier metal layer is formed so as to cover the entire first metal layer. That is, in this chip-type fuse, since the barrier metal layer is formed so as to cover the entire first metal layer, even if the second metal layer liquefies and flows out of the formation region significantly, it directly contacts the first metal layer. Can be prevented.

また、本発明のチップ型ヒューズは、前記バリア金属層が、第２金属層よりも低抵抗かつ高融点な金属で形成されていることを特徴とする。すなわち、このチップ型ヒューズでは、広いエリアに形成されたバリア金属層が第２金属層よりも低抵抗かつ高融点な金属で構成されているので、ヒューズ部全体の抵抗値を下げることができる。特に、バリア金属層が第１金属層の全体を覆って形成された場合は、ヒューズ部全体の抵抗値をより効果的に低減させることができる。   The chip type fuse of the present invention is characterized in that the barrier metal layer is made of a metal having a lower resistance and a higher melting point than the second metal layer. That is, in this chip-type fuse, since the barrier metal layer formed in a wide area is made of a metal having a lower resistance and a higher melting point than the second metal layer, the resistance value of the entire fuse portion can be lowered. In particular, when the barrier metal layer is formed so as to cover the entire first metal layer, the resistance value of the entire fuse portion can be more effectively reduced.

また、本発明のチップ型ヒューズは、前記第２金属層が、Ｓｎで形成され、前記バリア金属層が、Ａｇで形成されていることを特徴とする。すなわち、このチップ型ヒューズでは、第２金属層のＳｎよりも大幅に抵抗の低いＡｇでバリア金属層を形成しているので、ヒューズ部全体の抵抗値を顕著に低下させることができる。また、Ａｇは、従来のＮｉに比べてＳｎの拡散速度が大幅に速く、バリア金属層の構成金属として採用することにより速断性に優れるという利点がある。   In the chip-type fuse of the present invention, the second metal layer is made of Sn, and the barrier metal layer is made of Ag. That is, in this chip type fuse, the barrier metal layer is formed of Ag having a resistance much lower than Sn of the second metal layer, so that the resistance value of the entire fuse portion can be significantly reduced. Further, Ag has an advantage that Sn diffusion rate is significantly higher than that of conventional Ni, and it is excellent in quick disconnection when used as a constituent metal of the barrier metal layer.

本発明によれば、以下の効果を奏する。
すなわち、本発明に係るチップ型ヒューズによれば、バリア金属層が、第２金属層の形成領域よりも広い領域で形成されているので、第２金属層が液状化して形成領域から流れ出ても第１金属層に直接接触することを防ぐことができる。したがって、本発明によれば、安定した溶断時間が得られ、歩留まりを向上させることができる。 The present invention has the following effects.
That is, according to the chip-type fuse of the present invention, the barrier metal layer is formed in a region wider than the formation region of the second metal layer, so that even if the second metal layer liquefies and flows out of the formation region. Direct contact with the first metal layer can be prevented. Therefore, according to the present invention, a stable fusing time can be obtained and the yield can be improved.

以下、本発明に係るチップ型ヒューズの一実施形態を、図１から図５を参照しながら説明する。   Hereinafter, an embodiment of a chip-type fuse according to the present invention will be described with reference to FIGS.

本実施形態のチップ型ヒューズは、図１に示すように、絶縁基板１と、絶縁基板１の両端部に形成された一対の端面電極２と、絶縁基板１の上面に形成され一対の端面電極２に両端が接続された金属のヒューズ部４と、を備えている。なお、図１は、本実施形態のチップ型ヒューズの全体断面図であるが、ヒューズ部においてはヒューズ部に沿った断面を示している。
上記絶縁基板１は、絶縁性及び耐熱性が良好なアルミナセラミックス基板、ガラス基板又は樹脂基板等である。この絶縁基板１の裏面には、Ａｇ（銀）系樹脂（Ａｇペースト等）で形成された一対の裏面電極３が両端に設けられている。 As shown in FIG. 1, the chip-type fuse of the present embodiment includes an insulating substrate 1, a pair of end surface electrodes 2 formed on both ends of the insulating substrate 1, and a pair of end surface electrodes formed on the upper surface of the insulating substrate 1. 2 and a metal fuse portion 4 having both ends connected to each other. FIG. 1 is an overall cross-sectional view of the chip-type fuse of the present embodiment, and the fuse portion shows a cross section along the fuse portion.
The insulating substrate 1 is an alumina ceramic substrate, a glass substrate, a resin substrate, or the like having good insulation and heat resistance. On the back surface of the insulating substrate 1, a pair of back surface electrodes 3 formed of Ag (silver) resin (Ag paste or the like) is provided at both ends.

上記ヒューズ部４は、一対の端面電極２に両端が接続され銅箔で形成されたＣｕ層（第１金属層）５ａ及びＡｇめっきによるバリア金属層５ｂからなる第１エレメント５と、第１エレメント５の溶断部となる所定の中間部分に積層され第１エレメント５（Ｃｕ層５ａ及びバリア金属層５ｂ）よりも低融点な金属で形成された第２エレメント（第２金属層）６と、を備えている。すなわち、この第２エレメント６を構成する金属材料は、第１エレメント５の金属材料よりも融点が低く、第１エレメント５の金属材料と合金化することで、第１エレメント５の融点を下げるものが選択される。したがって、過電流が印加された場合、この第２エレメント６の形成箇所が溶断の主要部となる。なお、バリア金属層５ｂは、第２エレメント６の構成金属がＣｕ層５ａに拡散することを抑制する金属層として機能し、バリア金属層５ｂをＣｕ層５ａと第２エレメント６との間に形成しておくことで、速断性等の溶断特性を調整することができる。   The fuse portion 4 includes a first element 5 including a Cu layer (first metal layer) 5a formed of a copper foil and connected to a pair of end face electrodes 2 and a barrier metal layer 5b formed by Ag plating, and a first element. A second element (second metal layer) 6 that is laminated at a predetermined intermediate portion that becomes a fusing part 5 and is made of a metal having a melting point lower than that of the first element 5 (Cu layer 5a and barrier metal layer 5b). I have. That is, the metal material constituting the second element 6 has a lower melting point than the metal material of the first element 5, and lowers the melting point of the first element 5 by alloying with the metal material of the first element 5. Is selected. Therefore, when an overcurrent is applied, the location where the second element 6 is formed becomes the main part of fusing. The barrier metal layer 5b functions as a metal layer that suppresses the constituent metal of the second element 6 from diffusing into the Cu layer 5a, and the barrier metal layer 5b is formed between the Cu layer 5a and the second element 6. By doing so, it is possible to adjust the fusing characteristics such as quick-cutting properties.

上記第１エレメント５は、絶縁基板１上に、例えばエポキシ系樹脂シート、アクリル系樹脂シート又はシリコーン系樹脂シート等の接着シート７を介して設けられている。なお、第１エレメント５は、所望の溶断特性に合わせて厚さやパターン形状が決定される。また、第１エレメント５の両端には、端面電極２と接続された表面電極５ｃがパターン形成されている。   The first element 5 is provided on the insulating substrate 1 via an adhesive sheet 7 such as an epoxy resin sheet, an acrylic resin sheet, or a silicone resin sheet. Note that the thickness and pattern shape of the first element 5 are determined in accordance with desired fusing characteristics. In addition, a surface electrode 5 c connected to the end face electrode 2 is patterned at both ends of the first element 5.

また、バリア金属層５ｂは、第２エレメント６よりも低抵抗な金属で形成されている。すなわち、本実施形態では、第２エレメント６がＳｎ（錫）で形成され、バリア金属層５ｂがＡｇで形成されている。
また、バリア金属層５ｂは、第２エレメント６の形成領域よりも広い領域で形成されている。すなわち、本実施形態では、バリア金属層５ｂが、ヒューズ部４となるＣｕ層５ａの全体を覆って形成されている。
なお、本実施形態では、Ｃｕ層５ａを１μｍ〜１８μｍ、バリア金属層５ｂを０．１μｍ〜３μｍ、第２エレメント６を６μｍの厚さに設定している。 Further, the barrier metal layer 5 b is formed of a metal having a lower resistance than the second element 6. That is, in the present embodiment, the second element 6 is made of Sn (tin), and the barrier metal layer 5b is made of Ag.
The barrier metal layer 5 b is formed in a region wider than the region where the second element 6 is formed. That is, in the present embodiment, the barrier metal layer 5 b is formed so as to cover the entire Cu layer 5 a that becomes the fuse portion 4.
In this embodiment, the Cu layer 5a is set to a thickness of 1 μm to 18 μm, the barrier metal layer 5b is set to a thickness of 0.1 μm to 3 μm, and the second element 6 is set to a thickness of 6 μm.

上記接着シート７には、第１エレメント５の溶断部となる所定の中間部分が重なる領域に円形の切り欠き部７ａが形成されている。この切り欠き部７ａには、所定の耐熱性及び柔軟性を備えた下部樹脂８が充填されている。すなわち、下部樹脂８は、第１エレメント５の下部に接して配されている。さらに、第１エレメント５及び第２エレメント６上には、これらを覆うように上部樹脂９が形成されている。   In the adhesive sheet 7, a circular cutout portion 7 a is formed in a region where a predetermined intermediate portion serving as a fusing portion of the first element 5 overlaps. The notch 7a is filled with a lower resin 8 having predetermined heat resistance and flexibility. That is, the lower resin 8 is disposed in contact with the lower portion of the first element 5. Further, an upper resin 9 is formed on the first element 5 and the second element 6 so as to cover them.

下部樹脂８は、シリコーン系樹脂で形成され、上部樹脂９は、エポキシ系樹脂で形成されている。なお、上部樹脂９を、耐燃性、耐熱性及び熱伝導性に優れた珪酸をフィラーとして含有したエポキシ系樹脂や機械的強度や耐熱性に優れたアルミナをフィラーとして含有したエポキシ系樹脂で形成しても構わない。   The lower resin 8 is formed of a silicone resin, and the upper resin 9 is formed of an epoxy resin. The upper resin 9 is formed of an epoxy resin containing silicic acid having excellent flame resistance, heat resistance and thermal conductivity as a filler or an epoxy resin containing alumina having excellent mechanical strength and heat resistance as a filler. It doesn't matter.

また、上部樹脂９及び第１エレメント５上には、これらを覆うようにフィラー含有エポキシ系樹脂等の保護用樹脂１０が設けられている。
上記端面電極２は、導電性樹脂ペースト又はスパッタにより形成され、本実施形態では、Ａｇ系樹脂（Ａｇペースト等）で形成されている。また、端面電極２及び裏面電極３上には、これらを覆うようにＣｕ、Ｎｉ又はＳｎ等で端面電極メッキ部１１が形成されている。 A protective resin 10 such as a filler-containing epoxy resin is provided on the upper resin 9 and the first element 5 so as to cover them.
The end face electrode 2 is formed by a conductive resin paste or sputtering, and in this embodiment, is formed of an Ag-based resin (Ag paste or the like). On the end face electrode 2 and the back face electrode 3, an end face electrode plating portion 11 is formed of Cu, Ni, Sn, or the like so as to cover them.

次に、本実施形態のチップ型ヒューズの製造方法について、図２から図３を参照して説明する。   Next, a manufacturing method of the chip-type fuse of the present embodiment will be described with reference to FIGS.

まず、図２の（ａ）に示すように、絶縁基板１上に、切り欠き部７ａを予め形成した接着シート７をラミネート方式により貼り付ける。なお、予め切り欠き部７ａを形成せず、接着シート７を貼り付けた後に、切り欠き部７ａを形成しても構わない。次に、図２の（ｂ）に示すように、スクリーン印刷又はポッティングにより、切り欠き部７ａ内に、シリコーン系樹脂である下部樹脂８を充填する。   First, as shown in FIG. 2A, an adhesive sheet 7 in which a notch 7a is formed in advance is pasted on an insulating substrate 1 by a laminating method. Note that the cutout portion 7a may be formed after the adhesive sheet 7 is pasted without forming the cutout portion 7a in advance. Next, as shown in FIG. 2B, the lower resin 8 that is a silicone resin is filled into the cutout portion 7a by screen printing or potting.

そして、図２の（ｃ）に示すように、銅箔を接着シート７上にラミネート方式で貼り合わせ、さらに熱圧着することでＣｕ層５ａを形成する。なお、スパッタ等の薄膜プロセスを用いてＣｕ層５ａを形成しても構わない。次に、図２の（ｄ）に示すように、所望の溶断特性に合わせてフォトリソグラフィ技術によるパターンエッチングを施し、絶縁基板１の両端に位置する一対の表面電極５ｃを形成すると共に、表面電極５ｃを連結する所望の形状にＣｕ層５ａをパターン形成する。このとき、Ｃｕ層５ａを、切り欠き部７ａ上、すなわち下部樹脂８上の範囲内となるようにパターニングする。   Then, as shown in FIG. 2 (c), a copper foil is bonded onto the adhesive sheet 7 by a laminating method, and further thermocompression bonded to form a Cu layer 5a. Note that the Cu layer 5a may be formed using a thin film process such as sputtering. Next, as shown in FIG. 2 (d), pattern etching by photolithography is performed in accordance with desired fusing characteristics to form a pair of surface electrodes 5c positioned at both ends of the insulating substrate 1, and the surface electrodes The Cu layer 5a is patterned in a desired shape for connecting the 5c. At this time, the Cu layer 5a is patterned so as to be within the range on the notch 7a, that is, on the lower resin 8.

次に、図３の（ａ）に示すように、表面電極５ｃ及びＣｕ層５ａの上に、Ａｇめっきによりバリア金属層５ｂを形成する。この際、バリア金属層５ｂを、次工程で積層する第２エレメント６の形成領域よりも広い領域、すなわち、本実施形態では、ヒューズ部４となるＣｕ層５ａの全体を覆って形成されている。このようにして、Ｃｕ層５ａとバリア金属層５ｂとで第１エレメント５が構成される。さらに、図３の（ｂ）及び図４に示すように、第１エレメント５において溶断部となる所定の中間部分に、Ｓｎめっきにより第２エレメント６をパターニングして積層する。この際、上述したように、第２エレメント６の形成領域は、上記バリア金属層５ｂの形成領域より狭く設定される。
このように、第１エレメント５及び第２エレメント６によりヒューズ部４が構成される。 Next, as shown in FIG. 3A, a barrier metal layer 5b is formed on the surface electrode 5c and the Cu layer 5a by Ag plating. At this time, the barrier metal layer 5b is formed so as to cover a region wider than the formation region of the second element 6 to be laminated in the next step, that is, the entire Cu layer 5a serving as the fuse portion 4 in this embodiment. . Thus, the 1st element 5 is comprised by the Cu layer 5a and the barrier metal layer 5b. Further, as shown in FIG. 3B and FIG. 4, the second element 6 is patterned and laminated by Sn plating on a predetermined intermediate portion that becomes a fusing portion in the first element 5. At this time, as described above, the formation region of the second element 6 is set narrower than the formation region of the barrier metal layer 5b.
As described above, the first element 5 and the second element 6 constitute the fuse portion 4.

次に、図３の（ｃ）に示すように、ヒューズ部４上に、これを覆うようにスクリーン印刷等によりエポキシ系樹脂の上部樹脂９を形成し、さらに、その上にスクリーン印刷等によりフィラー含有エポキシ系樹脂等の保護用樹脂１０を形成する。そして、保護用樹脂１０形成後に、絶縁基板１の裏面に一対の裏面電極３を導電性樹脂の印刷硬化等によりパターン形成する。なお、第１エレメント５の形成前に裏面電極３を形成する場合は、メタルグレーズ系ペーストや金属有機物ペーストの印刷焼成等で形成することもできる。なお、ここまでの工程は、絶縁基板１を複数のチップ状に分割する以前の１枚の平板状態で複数を一括して処理する。   Next, as shown in FIG. 3C, an upper resin 9 made of epoxy resin is formed on the fuse portion 4 by screen printing or the like so as to cover it, and further a filler is formed thereon by screen printing or the like. A protective resin 10 such as a containing epoxy resin is formed. Then, after the protective resin 10 is formed, a pair of backside electrodes 3 are formed on the backside of the insulating substrate 1 by pattern-curing the conductive resin. In addition, when forming the back surface electrode 3 before formation of the 1st element 5, it can also form by printing baking etc. of a metal glaze paste or a metal organic substance paste. In addition, the process so far processes several collectively in the state of one flat plate before dividing | segmenting the insulated substrate 1 into several chip form.

そして、平板状態の絶縁基板１を短冊状に一次分割し、その絶縁基板１の端面に、Ａｇペーストの端面電極２を形成する。さらに、端面電極２及び裏面電極３上に、図３の（ｄ）に示すように、これらを覆うようにＣｕ、Ｎｉ又はＳｎめっき等で端面電極メッキ部１１を形成することで、本実施形態のチップ型ヒューズが作製される。   Then, the flat insulating substrate 1 is primarily divided into strips, and the end surface electrode 2 of Ag paste is formed on the end surface of the insulating substrate 1. Further, as shown in FIG. 3D, the end face electrode plating portion 11 is formed on the end face electrode 2 and the back face electrode 3 by Cu, Ni, Sn plating or the like so as to cover them. The chip type fuse is manufactured.

本実施形態のチップ型ヒューズでは、バリア金属層５ｂが、第２エレメント６の形成領域よりも広い領域で形成されているので、第２エレメント６が液状化して形成領域から流れ出てもＣｕ層５ａに直接接触することを抑制することができる。特に、バリア金属層５ｂがＣｕ層５ｂの全体を覆って形成されているので、第２エレメント６が液状化して形成領域から大幅に流れ出てもＣｕ層５ｂに直接接触することを防ぐことができる。   In the chip-type fuse of this embodiment, the barrier metal layer 5b is formed in a region wider than the region where the second element 6 is formed. Therefore, even if the second element 6 liquefies and flows out of the formation region, the Cu layer 5a It is possible to suppress direct contact with the surface. In particular, since the barrier metal layer 5b is formed so as to cover the entire Cu layer 5b, the second element 6 can be prevented from coming into direct contact with the Cu layer 5b even if the second element 6 liquefies and flows out of the formation region. .

また、広いエリアに形成されたバリア金属層５ｂが、第２エレメント６を構成するＳｎよりも高融点かつ大幅に低抵抗な金属であるＡｇで構成されているので、ヒューズ部４全体の抵抗値を大きく下げることができる。特に、バリア金属層５ｂがＣｕ層５ａの全体を覆って形成されているので、ヒューズ部４全体の抵抗値をより効果的に低減させることができる。
また、Ａｇは、Ｓｎの拡散速度を示す図５のグラフからわかるように、従来のＮｉに比べてＳｎの拡散速度が大幅に速く、バリア金属層５ｂの構成金属として採用することにより速断性に優れるという利点がある。 In addition, since the barrier metal layer 5b formed in a wide area is made of Ag, which is a metal having a higher melting point and significantly lower resistance than Sn constituting the second element 6, the resistance value of the entire fuse portion 4 Can be greatly reduced. In particular, since the barrier metal layer 5b is formed so as to cover the entire Cu layer 5a, the resistance value of the entire fuse portion 4 can be more effectively reduced.
Further, as can be seen from the graph of FIG. 5 showing the diffusion rate of Sn, Ag has a much faster diffusion rate of Sn than conventional Ni, and it can be quickly cut by adopting it as a constituent metal of the barrier metal layer 5b. There is an advantage of being excellent.

なお、本発明の技術範囲は上記実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。   The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

上記実施形態では、バリア金属層５ｂの構成金属として、Ａｇを採用しているが、第２エレメント６の構成金属であるＳｎよりも低抵抗な金属なら他の金属でも構わない。例えば、バリア金属層５ｂの構成金属として、Ｚｎ（亜鉛）、Ａｕ（金）、Ｃｒ（クロム）、Ｍｏ（モリブデン）、Ｔａ（タンタル）、Ｐｔ（白金）、Ｐｄ（パラジウム）等でも構わない。なお、上記構成金属のうちＺｎは、図５に示すように、Ｓｎの拡散速度が速く、Ａｇと同様に、バリア金属層５ｂの構成金属として採用することにより速断性に優れるという利点を有する。また、Ｓｎではなく、Ｐｂ−Ｓｎ（ハンダ）を第２エレメント６の構成金属に用いても構わない。   In the above embodiment, Ag is adopted as the constituent metal of the barrier metal layer 5b. However, other metals may be used as long as they are lower in resistance than Sn that is the constituent metal of the second element 6. For example, the constituent metal of the barrier metal layer 5b may be Zn (zinc), Au (gold), Cr (chromium), Mo (molybdenum), Ta (tantalum), Pt (platinum), Pd (palladium), or the like. As shown in FIG. 5, Zn among the above constituent metals has a high diffusion rate of Sn, and has the advantage of being excellent in quick disconnection when used as a constituent metal of the barrier metal layer 5b, similar to Ag. Further, instead of Sn, Pb—Sn (solder) may be used as a constituent metal of the second element 6.

本発明に係る一実施形態のチップ型ヒューズを示す断面図である。It is sectional drawing which shows the chip-type fuse of one Embodiment which concerns on this invention. 本実施形態のチップ型ヒューズの製造工程について、接着シートの貼り付けからＣｕ層のパターンエッチングまでを工程順に示す斜視図である。It is a perspective view which shows in order of a process from sticking of an adhesive sheet to pattern etching of Cu layer about the manufacturing process of the chip type fuse of this embodiment. 本実施形態のチップ型ヒューズの製造工程について、銀層（バリア金属層）の形成から端面電極メッキ部の形成までを工程順に示す斜視図である。It is a perspective view which shows in order of process from formation of a silver layer (barrier metal layer) to formation of an end surface electrode plating part about the manufacturing process of the chip-type fuse of this embodiment. 本実施形態のチップ型ヒューズについて、ヒューズ部に沿った要部の拡大断面図である。It is an expanded sectional view of the important section along a fuse part about a chip type fuse of this embodiment. 温度を横軸にしたＮｉ、Ａｇ及びＺｎに対するＳｎの拡散速度を示すグラフである。It is a graph which shows the diffusion rate of Sn with respect to Ni, Ag, and Zn which made temperature abscissa. 本発明に係る従来例について、ヒューズ部（ヒューズ膜）に沿った要部の拡大断面図である。It is an expanded sectional view of the principal part along the fuse part (fuse film) about the prior art example concerning the present invention.

符号の説明Explanation of symbols

１…絶縁基板、２…端面電極、３…裏面電極、４…ヒューズ部、５…第１エレメント、５ａ…Ｃｕ層（第１金属層）、５ｂ…バリア金属層、５ｃ…表面電極、６…第２エレメント（第２金属層）、８…下部樹脂、９…上部樹脂、１１…端面電極メッキ部
DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... End surface electrode, 3 ... Back electrode, 4 ... Fuse part, 5 ... 1st element, 5a ... Cu layer (1st metal layer), 5b ... Barrier metal layer, 5c ... Surface electrode, 6 ... 2nd element (2nd metal layer), 8 ... lower resin, 9 ... upper resin, 11 ... end face electrode plating part

Claims (4)

絶縁基板と、
前記絶縁基板の両端部に形成された一対の電極と、
前記絶縁基板の上面に形成され前記一対の電極に両端が接続された金属のヒューズ部と、を備え、
前記ヒューズ部が、前記一対の電極に両端が接続された第１金属層と、
前記第１金属層の所定の中間部分にバリア金属層を介して積層され前記第１金属層及び前記バリア金属層よりも低融点な金属で形成された第２金属層と、を備え、
前記バリア金属層が、前記第２金属層の形成領域よりも広い領域で形成されていることを特徴とするチップ型ヒューズ。 An insulating substrate;
A pair of electrodes formed on both ends of the insulating substrate;
A metal fuse portion formed on an upper surface of the insulating substrate and connected at both ends to the pair of electrodes, and
A first metal layer having both ends connected to the pair of electrodes;
A second metal layer formed of a metal having a melting point lower than that of the first metal layer and the barrier metal layer, and laminated on a predetermined intermediate portion of the first metal layer via a barrier metal layer;
The chip-type fuse, wherein the barrier metal layer is formed in an area wider than a formation area of the second metal layer. 請求項１に記載のチップ型ヒューズにおいて、
前記バリア金属層が、前記第１金属層の全体を覆って形成されていることを特徴とするチップ型ヒューズ。 The chip type fuse according to claim 1,
The chip-type fuse, wherein the barrier metal layer is formed so as to cover the entire first metal layer. 請求項１又は２に記載のチップ型ヒューズにおいて、
前記バリア金属層が、前記第２金属層よりも低抵抗かつ高融点な金属で形成されていることを特徴とするチップ型ヒューズ。 The chip-type fuse according to claim 1 or 2,
The chip-type fuse, wherein the barrier metal layer is formed of a metal having a lower resistance and a higher melting point than the second metal layer. 請求項３に記載のチップ型ヒューズにおいて、
前記第２金属層が、Ｓｎで形成され、
前記バリア金属層が、Ａｇで形成されていることを特徴とするチップ型ヒューズ。
The chip-type fuse according to claim 3,
The second metal layer is formed of Sn;
The chip-type fuse, wherein the barrier metal layer is made of Ag.
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WO2009019903A1 (en) * 2007-08-08 2009-02-12 Kamaya Electric Co., Ltd. Chip fuse and its manufacturing method
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EP2860750A1 (en) * 2013-10-11 2015-04-15 Littelfuse, Inc. Barrier layer to improve performance of electrical fuses utilizing the Metcalf effect
JP2015207550A (en) * 2014-04-08 2015-11-19 パナソニックＩｐマネジメント株式会社 Circuit protection element and manufacturing method for the same
JP2016004736A (en) * 2014-06-19 2016-01-12 Koa株式会社 Chip type fuse
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