CN101636808A - Chip fuse and manufacture method thereof - Google Patents
Chip fuse and manufacture method thereof Download PDFInfo
- Publication number
- CN101636808A CN101636808A CN200880000412A CN200880000412A CN101636808A CN 101636808 A CN101636808 A CN 101636808A CN 200880000412 A CN200880000412 A CN 200880000412A CN 200880000412 A CN200880000412 A CN 200880000412A CN 101636808 A CN101636808 A CN 101636808A
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- Prior art keywords
- recuperation layer
- fuse
- insulated substrate
- film
- recuperation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
- H01H85/05—Component parts thereof
- H01H85/055—Fusible members
- H01H85/08—Fusible members characterised by the shape or form of the fusible member
- H01H85/10—Fusible members characterised by the shape or form of the fusible member with constriction for localised fusing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H69/00—Apparatus or processes for the manufacture of emergency protective devices
- H01H69/02—Manufacture of fuses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/0039—Means for influencing the rupture process of the fusible element
- H01H85/0047—Heating means
- H01H85/006—Heat reflective or insulating layer on the casing or on the fuse support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/0039—Means for influencing the rupture process of the fusible element
- H01H85/0047—Heating means
- H01H85/0065—Heat reflective or insulating layer on the fusible element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
- H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
- H01H85/0411—Miniature fuses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
- H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
- H01H85/046—Fuses formed as printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/0241—Structural association of a fuse and another component or apparatus
- H01H2085/0283—Structural association with a semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
- H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
- H01H85/0411—Miniature fuses
- H01H2085/0414—Surface mounted fuses
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Fuses (AREA)
Abstract
The invention provides a kind of chip fuse, wherein the degree of freedom of operating chacteristics is not limited, and can prevent that the fusing time high with respect to the rated current multiplying power from shortening, and can make the chip fuse that shortens at the low fusing time of rated current multiplying power.In chip fuse (10), on insulated substrate (11), be formed with first recuperation layer (12) that constitutes by the lower membrane material of thermal conductivity, on first recuperation layer (12), be provided with fuse film (13) in the mode that does not contact with insulated substrate (11), fuse film (13) has fuse key element portion (13b) being disposed between the surface electrode portion (13a) at two ends, be formed with second recuperation layer (15) that is made of the lower membrane material of thermal conductivity in fuse key element portion (13b), first recuperation layer (12) forms thicklyer than second recuperation layer (15).First recuperation layer (12) and second recuperation layer (15) are formed by the flaky material of the B stage condition that contains the sensitization base.
Description
Technical field
The present invention relates to a kind of chip fuse and manufacture method thereof, relate more specifically to form the upper strata of fuse key element portion and chip fuse and the manufacture method thereof that lower floor forms by the lower film of thermal conductivity.
Background technology
About chip fuse,, for example, the technology of record in the patent documentation 1 is arranged as disclosed technology.Wherein on the upper surface of inorganic matter substrate, form silicone resin film, on this silicone resin film, form the fuse film, and, on this fuse film, form diaphragm by silicones, as the thickness of the silicone resin film of upper surface of base plate, example goes out 10 μ m.
In patent documentation 1, described by using silicones to prevent melt solder, burning with the connecting portion of printed wiring board, still, even stayed the material that changes fuse element and heat-conducting area etc., the also confined problem of the degree of freedom of operating chacteristics.
In addition, in the patent documentation 2 relevant with the method for making chip fuse, put down in writing the caloric value of utilizing fuse element and at around the balance of thermal discharge of member, decision is risen and is determined fusing time up to the temperature that fuses.And, put down in writing following content: the factor that influences this fusing time is resistance value, heat-conducting area, thermal conductivity, resistance value is the factor at caloric value, and, heat-conducting area and thermal conductivity are the factors at thermal discharge, for the degree of freedom of the operating chacteristics that improves chip fuse, need these factors of research.
But, in patent documentation 2,, do not study particularly about the material or the heat-conducting area of the member around the fuse element, and, open device or method do not had to controlling from the thermal discharge of the peripherad member of fuse element yet.
Patent documentation 1: the spy opens flat 11-96886 communique
Patent documentation 2: the spy opens flat 9-320445 communique
Summary of the invention
The present invention proposes in order to address the above problem, its objective is provides a kind of chip fuse and manufacture method thereof, the degree of freedom of operating chacteristics is not limited, can prevent that the fusing time under the high magnification from shortening with respect to rated current, and, can make at the fusing time under the low range of rated current to shorten.
In addition, the invention provides the manufacture method that can precision well and with comparalive ease forms the chip fuse of said chip fuse.
The present invention addresses the above problem by following scheme (1) to (3).
(1) a kind of chip fuse, on insulated substrate, be formed with first recuperation layer that constitutes by the low membrane material of thermal conductivity, on this first recuperation layer, be formed with the fuse film in the mode that does not contact with insulated substrate, this fuse film has fuse key element portion being disposed between the surface electrode portion at two ends, be formed with second recuperation layer that is made of the low membrane material of thermal conductivity in this fuse key element portion, described first recuperation layer forms than the described second accumulation of heat bed thickness.
(2) according to above-mentioned (1) described chip fuse, described first recuperation layer that is made of the low membrane material of thermal conductivity and described second recuperation layer are formed by the flaky material of B stage (B-stage) state (semi-harden state) that contains the sensitization base.
(3) a kind of manufacture method of chip fuse, in this chip fuse, on insulated substrate, be formed with first recuperation layer, on first recuperation layer, be formed with the fuse film, the fuse film has fuse key element portion being disposed between the surface electrode portion at two ends, in fuse key element portion, be formed with second recuperation layer, the method is characterized in that, comprise following operation: the containing the sensitization base and form the roughly flaky material of the B stage condition of homogeneous thickness (semi-harden state) of overlapping predetermined number on insulated substrate, form first recuperation layer; On first recuperation layer, form the fuse film in the mode that does not contact with insulated substrate, and, fuse key element portion between surface electrode portion, formed; At overlapping predetermined number between two surface electrode portions and the flaky material identical B stage condition of in described first recuperation layer, using, form second recuperation layer, wherein in forming the operation of described first recuperation layer, make the number of flaky material of overlapping B stage condition more than the operation of described second recuperation layer of formation.
In the present invention, constitute the lower membrane material of the thermal conductivity of first recuperation layer and second recuperation layer preferably thermal conductivity be membrane material about 0.1～0.4W/m ℃, for example, can use the flaky material of resin materials such as containing acrylate (acrylate) resin, epoxy resin and sensitization base to form.
In chip fuse of the present invention, the recuperation layer that constitutes by the low membrane material of thermal conductivity in fuse film upper and lower settings respectively, the recuperation layer of lower floor forms than the accumulation of heat bed thickness on upper strata, so, the degree of freedom of operating chacteristics is not limited, can prevent that the fusing time under the high magnification from shortening with respect to rated current, can make at the fusing time under the low range of rated current to shorten.
That is, thereby when the temperature of fuse key element portion that chip fuse is switched on rose, its heat passed to the below and is stored in first recuperation layer, and on the other hand, the heat that passes to the top is stored in second recuperation layer.Usually, insulated substrate is compared with air, the thermal conductivity height, so, make first recuperation layer form, thus, can suppress heat and escape into the below by insulated substrate from first recuperation layer than the second accumulation of heat bed thickness, thus, thus can be by shortening fusing time at the less low range lower seal heat of heat.In addition, utilization is compared with first recuperation layer to form and is obtained the second relatively thinner recuperation layer, release heat under the many high magnifications of heat, thus can prevent that fusing time from shortening.
In addition, in the manufacture method of chip fuse of the present invention, overlapping predetermined number forms the roughly flaky material of the B stage condition of homogeneous thickness on insulated substrate, form first recuperation layer, on the fuse film that is provided with on this first recuperation layer, the flaky material of the identical B stage condition of further overlapping predetermined number forms second recuperation layer.For these flaky materials, its thickness evenness is good, so, if adjust overlapping number, then can precision well and more easily first and second recuperation layer be formed desirable thickness.
Description of drawings
Fig. 1 (a)～(d) is the plane graph that the manufacture process of chip fuse is shown.
Fig. 2 (e)～(h) is the plane graph that illustrates with the continuous manufacture process of Fig. 1.
Fig. 3 (a) is the sectional view along the A-A line of Fig. 2, (b) is the sectional view along the B-B line of Fig. 2.
Fig. 4 is the chart of the operating chacteristics of chip fuse more of the present invention and conventional example.
Fig. 5 is the chart that the low range scope in the enlarged drawing 4 is shown.
Fig. 6 is the chart that the high magnification scope in the enlarged drawing 4 is shown.
Description of reference numerals
10 chip fuses
11 set insulated substrates
12 first recuperation layers
13 fuse films
13a surface electrode portion
13b fuse key element portion
14 fusing portions
15 second recuperation layers
Embodiment
Below, with reference to accompanying drawing one embodiment of the present invention is described, still, the invention is not restricted to this.
Fig. 1 (a)～(d) and Fig. 2 (e)～(h) are the plane graphs that the operation of making chip fuse 10 of the present invention is shown, Fig. 3 (a) is the sectional view along the chip fuse 10 of the A-A line of Fig. 2 (h), and Fig. 3 (b) is the sectional view along the chip fuse 10 of the B-B line of Fig. 2 (h).
In chip fuse 10, on insulated substrate 11, be formed with first recuperation layer 12 that constitutes by the lower membrane material of thermal conductivity, first recuperation layer 12 is provided with fuse film 13, fuse film 13 has the 13a of surface electrode portion that is configured in two ends and carries out the fuse key element 13b of portion that ways of connecting forms with narrow width with the 13a of surface electrode portion to these two ends, form Ni and Sn plated film or Sn plated film on the part of the 13a of surface electrode portion and the fuse key element 13b of portion whole, this plated film becomes fusing portion 14.And; in fusing portion 14; the zone wideer slightly than fusing portion 14 is provided with second recuperation layer 15 that is made of the lower membrane material of thermal conductivity; on second recuperation layer 15, be formed with protective layer 16; two ends at the back side of insulated substrate 11 are provided with back electrode 17; the both ends of the surface of insulated substrate 11 are provided with end electrode 18, and electrode plated film 19 is provided with in the mode of covering surfaces electrode 13a, end electrode 18 and back electrode 17.
At this, use aluminum oxide substrate as insulated substrate 11, in addition, the preferred lower membrane material of thermal conductivity that constitutes first recuperation layer 12 and second recuperation layer 15 is that thermal conductivity is the membrane material about 0.1～0.4W/m ℃, for example, can use the flaky material of B stage (B-stage) state (semi-harden state) about the thickness 30 μ m that contain resin materials such as acrylate (acrylate) resin, epoxy resin and sensitization base of predetermined number respectively.For example, if the flaky material of first recuperation layer, 12 overlapping two described B stage condition, second recuperation layer 15 uses the flaky material of an identical B stage condition to form, and then can form first recuperation layer 12 thicker than second recuperation layer 15.It is good at the resistance to chemical reagents of etching solution that this contains the material that forms after the flaky material sclerosis of B stage condition of resin material such as acrylate, epoxy resin and sensitization base, and thermal conductivity is lower.
For first recuperation layer 12, except the predetermined position of slot segmentation 11a of insulated substrate 11 and secondary splitting groove 11b, cover roughly whole of insulated substrate 11, the 12a of the portion of removing that this first recuperation layer 12 is removed is shape and the configuration of Fig. 1 (b) shown in (c), promptly is formed on the elongated scope of the predetermined length that strides across slot segmentation 11a and secondary splitting groove 11b.The mode of fuse film 13 not contact with insulated substrate 11 is stacked on first recuperation layer 12 with the shape layers shown in Fig. 1 (d).
As mentioned above, with 15 thicker than second recuperation layer, for example roughly the thickness of twice forms first recuperation layer 12, thus, the degree of freedom of operating chacteristics is not limited, can prevent that the fusing time under the high magnification from shortening with respect to rated current, and can make at the fusing time under the low range of rated current and shorten.
Next, illustrate that with reference to Fig. 1 and Fig. 2 rated current is the manufacture method of the chip fuse 10 of 1A.As the set insulated substrate that is used to make chip fuse, the purity of using aluminium oxide is about 96% aluminum oxide substrate.For chip fuse 10, on this set insulated substrate, form each structure of a plurality of layers, make thereby longitudinally and laterally cut off, Fig. 1 (a) (b) shown in a plurality of subregions of set on the insulated substrate, Fig. 1 (c) (d) and the subregion on the insulated substrate of set shown in Fig. 2 (e)～(h) promptly become the plane graph of the subregion of a chip fuse.
The groove of set insulated substrate is carved and is established operation
At first, utilize devices such as laser, on set insulated substrate 11, carve and establish slot segmentation 11a and the secondary splitting groove 11b that cuts off usefulness.Have in set to be pre-formed the once situation of slot segmentation 11a and secondary splitting groove 11b on the insulated substrate, under the situation of using such set insulated substrate, establish operation the quarter of omitting groove.
The formation operation of first recuperation layer
In order to form first recuperation layer 12, the flaky material of applying predetermined number on set insulated substrate 11.Flaky material uses resin materials such as comprising acrylate, epoxy resin and sensitization base and forms the flaky material of the B stage condition about thickness 30 μ m.In bonding process, the flaky material of this B stage condition is fitted on the set insulated substrate 11, is heated to predetermined temperature, after pressurizeing with predetermined pressure, further similarly another flaky material is pressurizeed while heating thereon, carry out overlapping applying.For two flaky materials after heating, the pressurization, bonding back thickness becomes about 56 μ m.Like this, overlap the flaky material of the B stage condition of predetermined number, thus, can adjust the thickness of first recuperation layer 12 with higher precision.
Next, on flaky material across photomask with ultraviolet 500mJ/cm
2After exposing, in sodium carbonate liquor 1wt%, soak a few minutes, flaky material is formed the shape that Fig. 1 (b) (c) illustrates.Thus, first recuperation layer 12 that the 12a of portion is removed is removed in formation on insulated substrate 11.
As flaky material, use the flaky material that comprises the sensitization base, implement above-mentioned operation, thereby can improve the dimensional accuracy of the flat shape of first recuperation layer 12, can reduce the deviation of operating chacteristics.
The formation operation of fuse film
On the set insulated substrate 11 that is formed with first recuperation layer 12, coating thickness is approximately electrolytic copper foil or the rolled copper foil about 3 μ m.This bonding process is undertaken by apply the predetermined pressure of the scheduled time under the temperature higher than normal temperature.Next, on electrolytic copper foil, stick the dry film of minus or apply aqueous resist, and from it after photomask exposes, the etching electrolytic copper foil is peeled off dry film or aqueous resist.Utilize operation as above, fuse film 13 is formed the flat shape shown in Fig. 1 (d).
The formation operation of fuse film fusing portion
At whole of the fuse key element 13b of portion of fuse film 13 with on the part of the continuous 13a of surface electrode portion in its both sides, utilize galvanoplastic that Ni and Sn plated film or Sn plated film are set, thus, form the fusing portion 14 shown in Fig. 2 (e), thus, provide M effect, obtain operating chacteristics fuse film 13.
The formation operation of second recuperation layer
Next, shown in Fig. 2 (f), form second recuperation layer 15 in the scope that all covers fusing portion 14.Second recuperation layer 15 also uses the flaky material that forms the B stage condition about the thickness 30 μ ms identical with first recuperation layer 12, this flaky material is fitted on the whole zone of set insulated substrate 11, carries out bonding with predetermined pressure while be heated to predetermined temperature.For this flaky material, after bonding, thickness becomes about 25 μ m.On the bonding flaky material, make ultraviolet exposure across photomask, afterwards, in sodium carbonate liquor, soak a few minutes, form the shape shown in Fig. 1 (g).
The formation operation of protective layer
Next, to cover the mode of second recuperation layer 15 fully, forming diaphragm 16 than its big slightly scope.Protective layer 16 is the films that formed by the epoxylite material by silk screen printing, and thus, disguise or mechanical strength improve.
The formation operation of back electrode, end electrode etc.
After forming protective layer 16, apply silver paste and carry out burn-back by silk screen print method at the back side of set insulated substrate 11, form back electrode 17.Next, cut off the set insulated substrate along a slot segmentation 11a, form the insulated substrate of rectangular shape, at the side coating silver paste of the long side direction of this rectangular shape insulated substrate and carry out burn-back or forms Cr film and Ni film by sputtering method, thus formation end electrode 18.And, cut off the rectangular shape insulated substrate along secondary splitting groove 11b, make each chip form, and form the electrode plated film 19 that constitutes by Cu film, Ni film and Sn film successively by barrel-plating, then as Fig. 2 (h) and shown in Figure 3, chip fuse 10 of the present invention is finished.
Next, Fig. 4 be comparison as the rated current of one embodiment of the present invention is the chart of operating chacteristics of the chip fuse of the chip fuse of 1A and comparative example.Fig. 5 is the chart that the low scope of rated transformation ratio in the enlarged drawing 4 is shown, and Fig. 6 is the chart that the high scope of rated transformation ratio in the enlarged drawing 4 is shown.
At this, sample C is an one embodiment of the present invention, and first recuperation layer forms about 60 μ m, and second recuperation layer forms about 30 μ m.
On the other hand, the chip fuse of sample A, B, D is a comparative example, and for any one sample, the relation of the relative thickness of first recuperation layer and second recuperation layer is different with chip fuse of the present invention, but structure in addition and chip fuse of the present invention are identically formed.First recuperation layer of sample A forms about 30 μ m, and second recuperation layer forms about 30 μ m.First recuperation layer of sample B forms about 30 μ m, and second recuperation layer forms about 60 μ m.First recuperation layer of sample D forms about 60 μ m, and second recuperation layer forms about 60 μ m.
To as the sample C of one embodiment of the present invention and sample D (first recuperation layer is the thickness identical with sample C) when comparing, in the low scope of rated transformation ratio, as shown in Figure 5, the fusing time of sample C is shorter than sample D.On the other hand, in the high scope of rated transformation ratio, as shown in Figure 6, the fusing time of sample C is longer than sample D.Hence one can see that, for chip fuse of the present invention, can prevent that the fusing time under the high magnification from shortening with respect to rated current, and make at the fusing time under the low range of rated current and shorten.
Claims (3)
1. chip fuse, wherein,
On insulated substrate, be formed with first recuperation layer that constitutes by the low membrane material of thermal conductivity, on this first recuperation layer, be formed with the fuse film in the mode that does not contact with insulated substrate, this fuse film has fuse key element portion being disposed between the surface electrode portion at two ends, be formed with second recuperation layer that is made of the low membrane material of thermal conductivity in this fuse key element portion, described first recuperation layer forms than the described second accumulation of heat bed thickness.
2. according to the chip fuse of claim 1, wherein,
Described first recuperation layer that is made of the low membrane material of thermal conductivity and described second recuperation layer are formed by the flaky material of the B stage condition that contains the sensitization base.
3. the manufacture method of a chip fuse, in this chip fuse, on insulated substrate, be formed with first recuperation layer, on first recuperation layer, be formed with the fuse film, the fuse film has fuse key element portion being disposed between the surface electrode portion at two ends, in fuse key element portion, be formed with second recuperation layer, the method is characterized in that
Comprise following operation: the containing the sensitization base and form the roughly flaky material of the B stage condition of homogeneous thickness of overlapping predetermined number on insulated substrate, form first recuperation layer; On first recuperation layer, form the fuse film in the mode that does not contact with insulated substrate, and, between surface electrode portion, form fuse key element portion; At overlapping predetermined number between two surface electrode portions and the flaky material identical B stage condition of in described first recuperation layer, using, form second recuperation layer,
In the operation that forms described first recuperation layer, the number of the flaky material of overlapping B stage condition is more than the operation that forms described second recuperation layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP036191/2008 | 2008-02-18 | ||
| JP2008036191A JP4612066B2 (en) | 2008-02-18 | 2008-02-18 | Chip fuse and manufacturing method thereof |
| PCT/JP2008/053550 WO2009104279A1 (en) | 2008-02-18 | 2008-02-28 | Chip fuse and process for producing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101636808A true CN101636808A (en) | 2010-01-27 |
| CN101636808B CN101636808B (en) | 2013-03-20 |
Family
ID=40985174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008800004128A Active CN101636808B (en) | 2008-02-18 | 2008-02-28 | Chip fuse and process for producing the same |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP4612066B2 (en) |
| KR (1) | KR101050243B1 (en) |
| CN (1) | CN101636808B (en) |
| TW (1) | TWI391974B (en) |
| WO (1) | WO2009104279A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944463A (en) * | 2010-08-31 | 2011-01-12 | 广东风华高新科技股份有限公司 | Film sheet fuse and preparation method thereof |
| CN103493168A (en) * | 2011-04-22 | 2014-01-01 | 双信电机株式会社 | Electric power fuse |
| CN114765084A (en) * | 2021-01-12 | 2022-07-19 | 国巨电子（中国）有限公司 | Fuse resistor and method of manufacturing the same |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5260592B2 (en) * | 2010-04-08 | 2013-08-14 | デクセリアルズ株式会社 | Protective element, battery control device, and battery pack |
| US9852868B2 (en) | 2012-09-28 | 2017-12-26 | Kamaya Electric Co., Ltd. | Chip fuse and manufacturing method therefor |
| CN106783448A (en) * | 2017-02-28 | 2017-05-31 | 中山市思福电子厂 | A kind of resistance-type coiling fuse and its manufacturing process |
| KR102095227B1 (en) | 2019-12-02 | 2020-03-31 | 장병철 | Manufacturing method of chip type fuse using thick film printing |
| KR102095225B1 (en) | 2019-12-02 | 2020-03-31 | 장병철 | Chip type fuse using hybrid intergrated circuit technology |
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| JPH0935614A (en) * | 1995-07-19 | 1997-02-07 | Hitachi Chem Co Ltd | Chip fuse and manufacture of it |
| JPH1050198A (en) * | 1996-07-30 | 1998-02-20 | Kyocera Corp | Chip fuse element |
| JPH10162714A (en) * | 1996-11-28 | 1998-06-19 | Kyocera Corp | Chip fuse element |
| EP1194023A4 (en) * | 1999-12-14 | 2005-11-09 | Matsushita Electric Ind Co Ltd | Multilayered printed wiring board and production method therefor |
| JP4369010B2 (en) * | 2000-04-12 | 2009-11-18 | 内橋エステック株式会社 | Temperature fuse |
| JP2003234057A (en) * | 2003-03-10 | 2003-08-22 | Koa Corp | Fuse resistor and its manufacturing method |
| JP4112417B2 (en) * | 2003-04-14 | 2008-07-02 | 釜屋電機株式会社 | Chip fuse and manufacturing method thereof |
| TW200719465A (en) * | 2005-11-11 | 2007-05-16 | Inpaq Technology Co Ltd | Chip type safety fuse and making method thereof |
-
2008
- 2008-02-18 JP JP2008036191A patent/JP4612066B2/en active Active
- 2008-02-28 KR KR1020087023427A patent/KR101050243B1/en active IP Right Grant
- 2008-02-28 CN CN2008800004128A patent/CN101636808B/en active Active
- 2008-02-28 WO PCT/JP2008/053550 patent/WO2009104279A1/en active Application Filing
-
2009
- 2009-02-18 TW TW098105128A patent/TWI391974B/en active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944463A (en) * | 2010-08-31 | 2011-01-12 | 广东风华高新科技股份有限公司 | Film sheet fuse and preparation method thereof |
| CN101944463B (en) * | 2010-08-31 | 2012-11-28 | 广东风华高新科技股份有限公司 | Film sheet fuse and preparation method thereof |
| CN103493168A (en) * | 2011-04-22 | 2014-01-01 | 双信电机株式会社 | Electric power fuse |
| CN114765084A (en) * | 2021-01-12 | 2022-07-19 | 国巨电子（中国）有限公司 | Fuse resistor and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20090115652A (en) | 2009-11-05 |
| KR101050243B1 (en) | 2011-07-19 |
| CN101636808B (en) | 2013-03-20 |
| JP4612066B2 (en) | 2011-01-12 |
| JP2009193927A (en) | 2009-08-27 |
| TW200945398A (en) | 2009-11-01 |
| TWI391974B (en) | 2013-04-01 |
| WO2009104279A1 (en) | 2009-08-27 |
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