JP2009158622A - 半導体記憶装置及びその製造方法 - Google Patents

半導体記憶装置及びその製造方法 Download PDF

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Publication number
JP2009158622A
JP2009158622A JP2007333306A JP2007333306A JP2009158622A JP 2009158622 A JP2009158622 A JP 2009158622A JP 2007333306 A JP2007333306 A JP 2007333306A JP 2007333306 A JP2007333306 A JP 2007333306A JP 2009158622 A JP2009158622 A JP 2009158622A
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Japan
Prior art keywords
insulating film
region
active region
semiconductor substrate
gate insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007333306A
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English (en)
Japanese (ja)
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JP2009158622A5 (enExample
Inventor
Toko Kato
陶子 加藤
Mitsuhiro Noguchi
充宏 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2007333306A priority Critical patent/JP2009158622A/ja
Priority to US12/338,417 priority patent/US8159019B2/en
Publication of JP2009158622A publication Critical patent/JP2009158622A/ja
Publication of JP2009158622A5 publication Critical patent/JP2009158622A5/ja
Priority to US13/426,664 priority patent/US8394689B2/en
Pending legal-status Critical Current

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    • H10P30/222—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/699—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having the gate at least partly formed in a trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Non-Volatile Memory (AREA)
JP2007333306A 2007-12-25 2007-12-25 半導体記憶装置及びその製造方法 Pending JP2009158622A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007333306A JP2009158622A (ja) 2007-12-25 2007-12-25 半導体記憶装置及びその製造方法
US12/338,417 US8159019B2 (en) 2007-12-25 2008-12-18 Semiconductor memory device with stacked gate including charge storage layer and control gate and method of manufacturing the same
US13/426,664 US8394689B2 (en) 2007-12-25 2012-03-22 Semiconductor memory device with stacked gate including charge storage layer and control gate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007333306A JP2009158622A (ja) 2007-12-25 2007-12-25 半導体記憶装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2009158622A true JP2009158622A (ja) 2009-07-16
JP2009158622A5 JP2009158622A5 (enExample) 2011-06-16

Family

ID=40787564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007333306A Pending JP2009158622A (ja) 2007-12-25 2007-12-25 半導体記憶装置及びその製造方法

Country Status (2)

Country Link
US (2) US8159019B2 (enExample)
JP (1) JP2009158622A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011003614A (ja) 2009-06-16 2011-01-06 Toshiba Corp 半導体記憶装置及びその製造方法
JP2011100946A (ja) * 2009-11-09 2011-05-19 Toshiba Corp 半導体記憶装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340791A (ja) * 1999-05-28 2000-12-08 Nec Corp 半導体装置の製造方法
JP2003060073A (ja) * 2001-08-10 2003-02-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2004349393A (ja) * 2003-05-21 2004-12-09 Renesas Technology Corp 半導体装置の製造方法
JP2007027622A (ja) * 2005-07-21 2007-02-01 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH104137A (ja) 1996-06-17 1998-01-06 Matsushita Electron Corp 半導体装置の製造方法
US6835987B2 (en) 2001-01-31 2004-12-28 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device in which selection gate transistors and memory cells have different structures
DE10131704A1 (de) * 2001-06-29 2003-01-16 Atmel Germany Gmbh Verfahren zur Dotierung eines Halbleiterkörpers
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US7550355B2 (en) * 2005-08-29 2009-06-23 Toshiba America Electronic Components, Inc. Low-leakage transistor and manufacturing method thereof
JP4959990B2 (ja) 2006-03-01 2012-06-27 株式会社東芝 半導体装置
TWI302355B (en) * 2006-04-20 2008-10-21 Promos Technologies Inc Method of fabricating a recess channel array transistor
JP2011003614A (ja) 2009-06-16 2011-01-06 Toshiba Corp 半導体記憶装置及びその製造方法
JP2011100946A (ja) 2009-11-09 2011-05-19 Toshiba Corp 半導体記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340791A (ja) * 1999-05-28 2000-12-08 Nec Corp 半導体装置の製造方法
JP2003060073A (ja) * 2001-08-10 2003-02-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2004349393A (ja) * 2003-05-21 2004-12-09 Renesas Technology Corp 半導体装置の製造方法
JP2007027622A (ja) * 2005-07-21 2007-02-01 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US20120178229A1 (en) 2012-07-12
US8394689B2 (en) 2013-03-12
US8159019B2 (en) 2012-04-17
US20090159961A1 (en) 2009-06-25

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