JP2008527739A5 - - Google Patents

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Publication number
JP2008527739A5
JP2008527739A5 JP2007551251A JP2007551251A JP2008527739A5 JP 2008527739 A5 JP2008527739 A5 JP 2008527739A5 JP 2007551251 A JP2007551251 A JP 2007551251A JP 2007551251 A JP2007551251 A JP 2007551251A JP 2008527739 A5 JP2008527739 A5 JP 2008527739A5
Authority
JP
Japan
Prior art keywords
dielectric layer
interconnect
covering cap
over
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007551251A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008527739A (ja
Filing date
Publication date
Priority claimed from US11/034,890 external-priority patent/US7105445B2/en
Application filed filed Critical
Publication of JP2008527739A publication Critical patent/JP2008527739A/ja
Publication of JP2008527739A5 publication Critical patent/JP2008527739A5/ja
Pending legal-status Critical Current

Links

JP2007551251A 2005-01-14 2005-12-02 被覆キャップを有する相互接続構造およびその製造方法 Pending JP2008527739A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/034,890 US7105445B2 (en) 2005-01-14 2005-01-14 Interconnect structures with encasing cap and methods of making thereof
PCT/US2005/043465 WO2006088534A1 (en) 2005-01-14 2005-12-02 Interconnect structures with encasing cap and methods of making thereof

Publications (2)

Publication Number Publication Date
JP2008527739A JP2008527739A (ja) 2008-07-24
JP2008527739A5 true JP2008527739A5 (enExample) 2008-10-09

Family

ID=36684497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007551251A Pending JP2008527739A (ja) 2005-01-14 2005-12-02 被覆キャップを有する相互接続構造およびその製造方法

Country Status (6)

Country Link
US (3) US7105445B2 (enExample)
EP (1) EP1836726A4 (enExample)
JP (1) JP2008527739A (enExample)
CN (1) CN100517621C (enExample)
TW (1) TW200634980A (enExample)
WO (1) WO2006088534A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7105445B2 (en) * 2005-01-14 2006-09-12 International Business Machines Corporation Interconnect structures with encasing cap and methods of making thereof
US7317253B2 (en) * 2005-04-25 2008-01-08 Sony Corporation Cobalt tungsten phosphate used to fill voids arising in a copper metallization process
US7737560B2 (en) * 2006-05-18 2010-06-15 Infineon Technologies Austria Ag Metallization layer for a power semiconductor device
US7582558B2 (en) * 2006-07-14 2009-09-01 Intel Corporation Reducing corrosion in copper damascene processes
US20090111263A1 (en) * 2007-10-26 2009-04-30 Kuan-Neng Chen Method of Forming Programmable Via Devices
US7998864B2 (en) * 2008-01-29 2011-08-16 International Business Machines Corporation Noble metal cap for interconnect structures
US8105937B2 (en) * 2008-08-13 2012-01-31 International Business Machines Corporation Conformal adhesion promoter liner for metal interconnects
US7803704B2 (en) * 2008-08-22 2010-09-28 Chartered Semiconductor Manufacturing, Ltd. Reliable interconnects
EP2345069B1 (en) * 2008-10-27 2016-02-17 Nxp B.V. Method of manufacturing a biocompatible electrode
US20110045171A1 (en) * 2009-08-19 2011-02-24 International Business Machines Corporation Multi-Step Method to Selectively Deposit Ruthenium Layers of Arbitrary Thickness on Copper
US8809183B2 (en) 2010-09-21 2014-08-19 International Business Machines Corporation Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer
US8492897B2 (en) 2011-09-14 2013-07-23 International Business Machines Corporation Microstructure modification in copper interconnect structures
US9711400B1 (en) 2016-06-07 2017-07-18 International Business Machines Corporation Interconnect structures with enhanced electromigration resistance
US10672653B2 (en) * 2017-12-18 2020-06-02 International Business Machines Corporation Metallic interconnect structures with wrap around capping layers
US12341100B2 (en) * 2021-10-11 2025-06-24 International Business Machines Corporation Copper interconnects with self-aligned hourglass-shaped metal cap
CN118338662A (zh) * 2023-01-03 2024-07-12 长鑫存储技术有限公司 半导体结构及其制作方法

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GB2257504B (en) * 1991-06-25 1995-10-25 Nec Semiconductors Method of measuring relative positioning accuracy of a pattern to be formed on a semiconductor wafer
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
WO1996002070A2 (en) * 1994-07-12 1996-01-25 National Semiconductor Corporation Integrated circuit comprising a trench isolation structure and an oxygen barrier layer and method for forming the integrated circuit
JP2985692B2 (ja) * 1994-11-16 1999-12-06 日本電気株式会社 半導体装置の配線構造及びその製造方法
US6294799B1 (en) * 1995-11-27 2001-09-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating same
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6215129B1 (en) * 1997-12-01 2001-04-10 Vsli Technology, Inc. Via alignment, etch completion, and critical dimension measurement method and structure
US6103625A (en) * 1997-12-31 2000-08-15 Intel Corporation Use of a polish stop layer in the formation of metal structures
US6157081A (en) * 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
JP2000323479A (ja) * 1999-05-14 2000-11-24 Sony Corp 半導体装置およびその製造方法
JP3626058B2 (ja) * 2000-01-25 2005-03-02 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US6391669B1 (en) * 2000-06-21 2002-05-21 International Business Machines Corporation Embedded structures to provide electrical testing for via to via and interface layer alignment as well as for conductive interface electrical integrity in multilayer devices
TW463307B (en) * 2000-06-29 2001-11-11 Mosel Vitelic Inc Manufacturing method of dual damascene structure
US6461963B1 (en) * 2000-08-30 2002-10-08 Micron Technology, Inc. Utilization of disappearing silicon hard mask for fabrication of semiconductor structures
JP2002111185A (ja) * 2000-10-03 2002-04-12 Sony Chem Corp バンプ付き配線回路基板及びその製造方法
JP4169950B2 (ja) * 2001-05-18 2008-10-22 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP2003179058A (ja) * 2001-12-12 2003-06-27 Sony Corp 半導体装置の製造方法
US6605874B2 (en) * 2001-12-19 2003-08-12 Intel Corporation Method of making semiconductor device using an interconnect
US20030116439A1 (en) * 2001-12-21 2003-06-26 International Business Machines Corporation Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices
JP2003243389A (ja) * 2002-02-15 2003-08-29 Sony Corp 半導体装置及びその製造方法
JP4103497B2 (ja) * 2002-04-18 2008-06-18 ソニー株式会社 記憶装置とその製造方法および使用方法、半導体装置とその製造方法
JP3935049B2 (ja) * 2002-11-05 2007-06-20 株式会社東芝 磁気記憶装置及びその製造方法
US6764919B2 (en) * 2002-12-20 2004-07-20 Motorola, Inc. Method for providing a dummy feature and structure thereof
FR2857719B1 (fr) * 2003-07-17 2006-02-03 Snecma Moteurs Dispositif de vanne a longue course de regulation
US6838355B1 (en) * 2003-08-04 2005-01-04 International Business Machines Corporation Damascene interconnect structures including etchback for low-k dielectric materials
JP4207749B2 (ja) * 2003-10-28 2009-01-14 沖電気工業株式会社 半導体装置の配線構造及びその製造方法
US7105445B2 (en) * 2005-01-14 2006-09-12 International Business Machines Corporation Interconnect structures with encasing cap and methods of making thereof

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