CN100517621C - 具有包覆层的互连结构及其制造方法 - Google Patents
具有包覆层的互连结构及其制造方法 Download PDFInfo
- Publication number
- CN100517621C CN100517621C CN200580046544.0A CN200580046544A CN100517621C CN 100517621 C CN100517621 C CN 100517621C CN 200580046544 A CN200580046544 A CN 200580046544A CN 100517621 C CN100517621 C CN 100517621C
- Authority
- CN
- China
- Prior art keywords
- coating layer
- dielectric material
- interconnection structure
- interconnection
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (22)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/034,890 US7105445B2 (en) | 2005-01-14 | 2005-01-14 | Interconnect structures with encasing cap and methods of making thereof |
US11/034,890 | 2005-01-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101099235A CN101099235A (zh) | 2008-01-02 |
CN100517621C true CN100517621C (zh) | 2009-07-22 |
Family
ID=36684497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200580046544.0A Expired - Fee Related CN100517621C (zh) | 2005-01-14 | 2005-12-02 | 具有包覆层的互连结构及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (3) | US7105445B2 (zh) |
EP (1) | EP1836726A4 (zh) |
JP (1) | JP2008527739A (zh) |
CN (1) | CN100517621C (zh) |
TW (1) | TW200634980A (zh) |
WO (1) | WO2006088534A1 (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7105445B2 (en) * | 2005-01-14 | 2006-09-12 | International Business Machines Corporation | Interconnect structures with encasing cap and methods of making thereof |
US7317253B2 (en) * | 2005-04-25 | 2008-01-08 | Sony Corporation | Cobalt tungsten phosphate used to fill voids arising in a copper metallization process |
US7737560B2 (en) * | 2006-05-18 | 2010-06-15 | Infineon Technologies Austria Ag | Metallization layer for a power semiconductor device |
US7582558B2 (en) * | 2006-07-14 | 2009-09-01 | Intel Corporation | Reducing corrosion in copper damascene processes |
US20090111263A1 (en) * | 2007-10-26 | 2009-04-30 | Kuan-Neng Chen | Method of Forming Programmable Via Devices |
US7998864B2 (en) * | 2008-01-29 | 2011-08-16 | International Business Machines Corporation | Noble metal cap for interconnect structures |
US8105937B2 (en) * | 2008-08-13 | 2012-01-31 | International Business Machines Corporation | Conformal adhesion promoter liner for metal interconnects |
US7803704B2 (en) * | 2008-08-22 | 2010-09-28 | Chartered Semiconductor Manufacturing, Ltd. | Reliable interconnects |
US9281239B2 (en) * | 2008-10-27 | 2016-03-08 | Nxp B.V. | Biocompatible electrodes and methods of manufacturing biocompatible electrodes |
US20110045171A1 (en) * | 2009-08-19 | 2011-02-24 | International Business Machines Corporation | Multi-Step Method to Selectively Deposit Ruthenium Layers of Arbitrary Thickness on Copper |
US8809183B2 (en) | 2010-09-21 | 2014-08-19 | International Business Machines Corporation | Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer |
US8492897B2 (en) | 2011-09-14 | 2013-07-23 | International Business Machines Corporation | Microstructure modification in copper interconnect structures |
US9711400B1 (en) | 2016-06-07 | 2017-07-18 | International Business Machines Corporation | Interconnect structures with enhanced electromigration resistance |
US10672653B2 (en) * | 2017-12-18 | 2020-06-02 | International Business Machines Corporation | Metallic interconnect structures with wrap around capping layers |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2257504B (en) * | 1991-06-25 | 1995-10-25 | Nec Semiconductors | Method of measuring relative positioning accuracy of a pattern to be formed on a semiconductor wafer |
US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
WO1996002070A2 (en) * | 1994-07-12 | 1996-01-25 | National Semiconductor Corporation | Integrated circuit comprising a trench isolation structure and an oxygen barrier layer and method for forming the integrated circuit |
JP2985692B2 (ja) * | 1994-11-16 | 1999-12-06 | 日本電気株式会社 | 半導体装置の配線構造及びその製造方法 |
US6294799B1 (en) * | 1995-11-27 | 2001-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating same |
US5695810A (en) * | 1996-11-20 | 1997-12-09 | Cornell Research Foundation, Inc. | Use of cobalt tungsten phosphide as a barrier material for copper metallization |
US6215129B1 (en) * | 1997-12-01 | 2001-04-10 | Vsli Technology, Inc. | Via alignment, etch completion, and critical dimension measurement method and structure |
US6103625A (en) * | 1997-12-31 | 2000-08-15 | Intel Corporation | Use of a polish stop layer in the formation of metal structures |
US6157081A (en) * | 1999-03-10 | 2000-12-05 | Advanced Micro Devices, Inc. | High-reliability damascene interconnect formation for semiconductor fabrication |
JP2000323479A (ja) * | 1999-05-14 | 2000-11-24 | Sony Corp | 半導体装置およびその製造方法 |
JP3626058B2 (ja) * | 2000-01-25 | 2005-03-02 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6391669B1 (en) * | 2000-06-21 | 2002-05-21 | International Business Machines Corporation | Embedded structures to provide electrical testing for via to via and interface layer alignment as well as for conductive interface electrical integrity in multilayer devices |
TW463307B (en) * | 2000-06-29 | 2001-11-11 | Mosel Vitelic Inc | Manufacturing method of dual damascene structure |
US6461963B1 (en) * | 2000-08-30 | 2002-10-08 | Micron Technology, Inc. | Utilization of disappearing silicon hard mask for fabrication of semiconductor structures |
JP4169950B2 (ja) * | 2001-05-18 | 2008-10-22 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2003179058A (ja) * | 2001-12-12 | 2003-06-27 | Sony Corp | 半導体装置の製造方法 |
US6605874B2 (en) * | 2001-12-19 | 2003-08-12 | Intel Corporation | Method of making semiconductor device using an interconnect |
US20030116439A1 (en) * | 2001-12-21 | 2003-06-26 | International Business Machines Corporation | Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices |
JP2003243389A (ja) * | 2002-02-15 | 2003-08-29 | Sony Corp | 半導体装置及びその製造方法 |
JP4103497B2 (ja) * | 2002-04-18 | 2008-06-18 | ソニー株式会社 | 記憶装置とその製造方法および使用方法、半導体装置とその製造方法 |
JP3935049B2 (ja) * | 2002-11-05 | 2007-06-20 | 株式会社東芝 | 磁気記憶装置及びその製造方法 |
US6764919B2 (en) * | 2002-12-20 | 2004-07-20 | Motorola, Inc. | Method for providing a dummy feature and structure thereof |
FR2857719B1 (fr) * | 2003-07-17 | 2006-02-03 | Snecma Moteurs | Dispositif de vanne a longue course de regulation |
US6838355B1 (en) * | 2003-08-04 | 2005-01-04 | International Business Machines Corporation | Damascene interconnect structures including etchback for low-k dielectric materials |
JP4207749B2 (ja) * | 2003-10-28 | 2009-01-14 | 沖電気工業株式会社 | 半導体装置の配線構造及びその製造方法 |
US7105445B2 (en) * | 2005-01-14 | 2006-09-12 | International Business Machines Corporation | Interconnect structures with encasing cap and methods of making thereof |
-
2005
- 2005-01-14 US US11/034,890 patent/US7105445B2/en not_active Expired - Fee Related
- 2005-12-02 EP EP05852629A patent/EP1836726A4/en not_active Withdrawn
- 2005-12-02 WO PCT/US2005/043465 patent/WO2006088534A1/en active Application Filing
- 2005-12-02 JP JP2007551251A patent/JP2008527739A/ja active Pending
- 2005-12-02 CN CN200580046544.0A patent/CN100517621C/zh not_active Expired - Fee Related
-
2006
- 2006-01-04 TW TW095100294A patent/TW200634980A/zh unknown
- 2006-08-14 US US11/503,259 patent/US7488677B2/en not_active Expired - Fee Related
-
2008
- 2008-08-27 US US12/199,407 patent/US7902061B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20070054489A1 (en) | 2007-03-08 |
EP1836726A4 (en) | 2010-07-28 |
JP2008527739A (ja) | 2008-07-24 |
US20080318415A1 (en) | 2008-12-25 |
US7105445B2 (en) | 2006-09-12 |
US20060160349A1 (en) | 2006-07-20 |
WO2006088534A1 (en) | 2006-08-24 |
US7902061B2 (en) | 2011-03-08 |
TW200634980A (en) | 2006-10-01 |
EP1836726A1 (en) | 2007-09-26 |
CN101099235A (zh) | 2008-01-02 |
US7488677B2 (en) | 2009-02-10 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171101 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171101 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
|
TR01 | Transfer of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090722 Termination date: 20191202 |
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CF01 | Termination of patent right due to non-payment of annual fee |