JP2008519436A - 充填酸化物層が蒸着されたトレンチを有するmosfet - Google Patents
充填酸化物層が蒸着されたトレンチを有するmosfet Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 72
- 238000007740 vapor deposition Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 20
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims 4
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000007943 implant Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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Abstract
【解決手段】P型またはN型の導電型を有するドリフト領域、およびこのドリフト領域の上にあって、ドリフト領域と反対の導電型を有するチャネル領域を含む半導体層と、 前記チャネル領域を貫通して前記半導体層に形成されたゲートトレンチと、前記ゲートトレンチの底部に形成されたゲート充填酸化物層と、前記ゲート充填酸化物層上に形成されたゲート電極と、前記トレンチの側壁と前記ゲート電極の間に挾まれ、かつゲート電極よりも密度が小さいゲート酸化膜とを備えるパワー半導体デバイス。
【選択図】図1
Description
12 半導体基板
14 半導体層
16 ドリフト領域
18 チャネル領域
20 導電領域
22 ゲートトレンチ
24 ゲート充填酸化物層
25 ゲート電極
28 ゲート酸化膜
30 第1の電極
32 シリサイド層
34 第2の電極
36 フィールドレリーフトレンチ
38 フィールド充填酸化物層
40 凹部
42 フィールド電極
44 高導電領域
46 チャネルインプラント領域
48 パッド酸化物層
50 マスク
52 犠牲層
54 酸化物層
56 窒化物層
58 スペーサ
60 ゲート保護マスク
62 ポリシリコン層
64 TEOS層
66 ゲート保護マスク
Claims (19)
- P型またはN型の導電型を有するドリフト領域、およびこのドリフト領域の上にあって、ドリフト領域と反対の導電型を有するチャネル領域を含む半導体層と、
前記チャネル領域を貫通して前記半導体層に形成されたゲートトレンチと、
前記ゲートトレンチの底部に形成されたゲート充填酸化物層と、
前記ゲート充填酸化物層上に形成されたゲート電極と、
前記トレンチの側壁と前記ゲート電極の間に挾まれ、かつゲート電極よりも密度が小さいゲート酸化膜とを備えるパワー半導体デバイス。 - 前記ゲート充填酸化物層は、TEOS(テトラエトキシシラン)からなることを特徴とする請求項1記載のパワー半導体デバイス。
- 前記ゲート充填酸化物層は蒸着によって形成されたものであり、前記ゲート酸化膜は酸化による成長によって形成されたものであることを特徴とする請求項1記載のパワー半導体デバイス。
- 凹部をもつフィールド充填酸化物層と、前記凹部に一部が収容された断面T字形の電極とを有するフィールドレリーフトレンチをさらに備えることを特徴とする請求項1記載のパワー半導体デバイス。
- 前記断面T字形の電極と電気的に接続されたもう1つの電極をさらに備えることを特徴とする請求項4記載のパワー半導体デバイス。
- 前記半導体層と前記もう1つの電極との間に、ケイ化物層をさらに備えることを特徴とする請求項5記載のパワー半導体デバイス。
- 前記断面T字形の電極と前記もう1つの電極との間に、ケイ化物層をさらに備えることを特徴とする請求項5記載のパワー半導体デバイス。
- フィールド充填酸化物層、およびこのフィールド充填酸化物層内に形成されたフィールド電極を有するフィールドレリーフトレンチと、前記チャネル領域と同一の導電型をもち、かつチャネル領域の側方に形成された高導電領域と、前記フィールド電極および前記高導電領域と電気的に接続されたもう1つの電極とをさらに備えることを特徴とする請求項1記載のパワー半導体デバイス。
- 前記ゲート電極を覆う酸化物キャップをさらに備えることを特徴とする請求項1記載のパワー半導体デバイス。
- 半導体層に、トレンチを形成する工程と、前記トレンチの底部に酸化物層を蒸着する工程と、前記酸化物層上に電極を形成する工程とを含むパワー半導体デバイスの製造方法。
- 前記電極を形成する工程の前に、前記トレンチの側壁に酸化膜を成長させる工程をさらに含むことを特徴とする請求項10記載の方法。
- 前記充填酸化物層を覆うように、前記トレンチの各側壁にスペーサを形成する工程と、前記充填酸化物層に凹部を形成するため、この充填酸化物層の一部を除去する工程とをさらに含むことを特徴とする請求項10記載の方法。
- 前記凹部を充填するため、前記トレンチの内部に導電体を蒸着する工程と、このトレンチに断面T字形の電極を形成するため、前記導電体の一部を除去する工程とをさらに含むことを特徴とする請求項12記載の方法。
- 複数のフィールドレリーフトレンチを形成する工程と、前記フィールドレリーフトレンチの底部に、フィールド充填酸化物層を形成する工程と、前記フィールド充填酸化物層を覆うように、各フィールドレリーフトレンチの側壁にスペーサを形成する工程と、前記フィールド充填酸化物層に凹部を形成するため、このフィールド酸化物層の一部を除去する工程とをさらに含むことを特徴とする請求項10記載の方法。
- 前記凹部を充填するため、前記フィールドレリーフトレンチの内部に導電体を蒸着する工程と、このフィールドレリーフトレンチに断面T字形の電極を形成するため、前記導電体の一部を除去する工程とをさらに含むことを特徴とする請求項14記載の方法。
- 前記半導体層をケイ化する工程と、このケイ化された半導体層の一部と電気的接続をとる工程とをさらに含むことを特徴とする請求項15記載の方法。
- 前記断面T字形電極の一部をケイ化する工程をさらに含むことを特徴とする請求項16記載の方法。
- 前記フィールドレリーフトレンチの側方に高導電領域を形成する工程と、この高導電領域と電気的接続をとる工程をさらに含むことを特徴とする請求項14記載の方法。
- 前記フィールドレリーフトレンチの側方に高導電領域を形成する工程と、この高導電領域と電気的接続をとる工程をさらに含むことを特徴とする請求項10記載の方法。
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US62367904P | 2004-10-29 | 2004-10-29 | |
US60/623,679 | 2004-10-29 | ||
US11/261,896 US7371641B2 (en) | 2004-10-29 | 2005-10-28 | Method of making a trench MOSFET with deposited oxide |
US11/261,896 | 2005-10-28 | ||
PCT/US2005/039132 WO2006050192A2 (en) | 2004-10-29 | 2005-10-31 | Trench mosfet with deposited oxide |
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JP2008519436A true JP2008519436A (ja) | 2008-06-05 |
JP5336738B2 JP5336738B2 (ja) | 2013-11-06 |
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JP2007539209A Active JP5336738B2 (ja) | 2004-10-29 | 2005-10-31 | パワー半導体デバイスおよびその製造方法 |
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US (2) | US7371641B2 (ja) |
JP (1) | JP5336738B2 (ja) |
CN (1) | CN101164149B (ja) |
WO (1) | WO2006050192A2 (ja) |
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JP2014187226A (ja) * | 2013-03-25 | 2014-10-02 | Toshiba Corp | 半導体装置 |
WO2014171210A1 (ja) * | 2013-04-16 | 2014-10-23 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法および炭化珪素半導体装置 |
WO2014171211A1 (ja) * | 2013-04-16 | 2014-10-23 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
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US7400014B2 (en) | 2004-04-20 | 2008-07-15 | International Rectifier Corporation | ACCUFET with schottky source contact |
US9685524B2 (en) | 2005-03-11 | 2017-06-20 | Vishay-Siliconix | Narrow semiconductor trench structure |
TWI489557B (zh) | 2005-12-22 | 2015-06-21 | Vishay Siliconix | 高移動率p-通道溝槽及平面型空乏模式的功率型金屬氧化物半導體場效電晶體 |
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US20100013009A1 (en) * | 2007-12-14 | 2010-01-21 | James Pan | Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance |
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CN102184959B (zh) * | 2011-04-25 | 2016-03-02 | 上海华虹宏力半导体制造有限公司 | 功率mos管及其制造方法 |
CN102420152A (zh) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | 一种用于功率器件在线控制沟槽剩余氧化硅厚度的方法 |
US8502302B2 (en) | 2011-05-02 | 2013-08-06 | Alpha And Omega Semiconductor Incorporated | Integrating Schottky diode into power MOSFET |
MY162310A (en) | 2011-06-02 | 2017-05-31 | Silterra Malaysia Sdn Bhd | Method for fabricating a bottom oxide layer in a trench |
US9412883B2 (en) | 2011-11-22 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for MOS capacitors in replacement gate process |
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US20140110777A1 (en) | 2012-10-18 | 2014-04-24 | United Microelectronics Corp. | Trench gate metal oxide semiconductor field effect transistor and fabricating method thereof |
TW201423869A (zh) * | 2012-12-13 | 2014-06-16 | Anpec Electronics Corp | 溝渠式電晶體的製作方法 |
DE102015202764B4 (de) | 2015-02-16 | 2018-05-30 | Infineon Technologies Austria Ag | Verfahren zur Herstellung einer Graben-Halbleitervorrichtung mit einem Isolierblock in einem Halbleitergraben und Halbleitervorrichtung |
TWI706452B (zh) | 2019-04-11 | 2020-10-01 | 台灣茂矽電子股份有限公司 | 閘結構之製造方法及閘結構 |
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2005
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- 2005-10-31 CN CN2005800375514A patent/CN101164149B/zh not_active Expired - Fee Related
- 2005-10-31 WO PCT/US2005/039132 patent/WO2006050192A2/en active Application Filing
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Cited By (6)
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JP2014187226A (ja) * | 2013-03-25 | 2014-10-02 | Toshiba Corp | 半導体装置 |
US8981462B2 (en) | 2013-03-25 | 2015-03-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
WO2014171210A1 (ja) * | 2013-04-16 | 2014-10-23 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法および炭化珪素半導体装置 |
WO2014171211A1 (ja) * | 2013-04-16 | 2014-10-23 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
US9627487B2 (en) | 2013-04-16 | 2017-04-18 | Sumitomo Electric Industries, Ltd. | Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device |
US9793365B2 (en) | 2013-04-16 | 2017-10-17 | Sumitomo Electric Industries, Ltd. | Method for manufacturing silicon carbide semiconductor device having trench |
Also Published As
Publication number | Publication date |
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US20060091456A1 (en) | 2006-05-04 |
US20080185642A1 (en) | 2008-08-07 |
US8106446B2 (en) | 2012-01-31 |
JP5336738B2 (ja) | 2013-11-06 |
WO2006050192A2 (en) | 2006-05-11 |
CN101164149B (zh) | 2010-11-03 |
CN101164149A (zh) | 2008-04-16 |
WO2006050192A3 (en) | 2007-12-27 |
US7371641B2 (en) | 2008-05-13 |
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