JP2008514001A5 - - Google Patents

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Publication number
JP2008514001A5
JP2008514001A5 JP2007532343A JP2007532343A JP2008514001A5 JP 2008514001 A5 JP2008514001 A5 JP 2008514001A5 JP 2007532343 A JP2007532343 A JP 2007532343A JP 2007532343 A JP2007532343 A JP 2007532343A JP 2008514001 A5 JP2008514001 A5 JP 2008514001A5
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JP
Japan
Prior art keywords
metal layer
forming
etching
layer
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007532343A
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English (en)
Japanese (ja)
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JP2008514001A (ja
JP4891906B2 (ja
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Publication date
Priority claimed from US10/943,383 external-priority patent/US7208424B2/en
Application filed filed Critical
Publication of JP2008514001A publication Critical patent/JP2008514001A/ja
Publication of JP2008514001A5 publication Critical patent/JP2008514001A5/ja
Application granted granted Critical
Publication of JP4891906B2 publication Critical patent/JP4891906B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007532343A 2004-09-17 2005-08-23 金属層を有する半導体素子の形成方法 Expired - Fee Related JP4891906B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/943,383 US7208424B2 (en) 2004-09-17 2004-09-17 Method of forming a semiconductor device having a metal layer
US10/943,383 2004-09-17
PCT/US2005/029772 WO2006033746A2 (en) 2004-09-17 2005-08-23 Method of forming a semiconductor device having a metal layer

Publications (3)

Publication Number Publication Date
JP2008514001A JP2008514001A (ja) 2008-05-01
JP2008514001A5 true JP2008514001A5 (https=) 2008-10-09
JP4891906B2 JP4891906B2 (ja) 2012-03-07

Family

ID=36074612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007532343A Expired - Fee Related JP4891906B2 (ja) 2004-09-17 2005-08-23 金属層を有する半導体素子の形成方法

Country Status (4)

Country Link
US (1) US7208424B2 (https=)
JP (1) JP4891906B2 (https=)
KR (1) KR20070057844A (https=)
WO (1) WO2006033746A2 (https=)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7354847B2 (en) * 2004-01-26 2008-04-08 Taiwan Semiconductor Manufacturing Company Method of trimming technology
KR100562657B1 (ko) * 2004-12-29 2006-03-20 주식회사 하이닉스반도체 리세스게이트 및 그를 구비한 반도체장치의 제조 방법
US7435681B2 (en) * 2006-05-09 2008-10-14 Macronix International Co., Ltd. Methods of etching stacks having metal layers and hard mask layers
JP5578389B2 (ja) * 2006-05-16 2014-08-27 Ｎｌｔテクノロジー株式会社 積層膜パターン形成方法及びゲート電極形成方法
US7655550B2 (en) * 2006-06-30 2010-02-02 Freescale Semiconductor, Inc. Method of making metal gate transistors
US8394724B2 (en) * 2006-08-31 2013-03-12 Globalfoundries Singapore Pte. Ltd. Processing with reduced line end shortening ratio
US7977218B2 (en) * 2006-12-26 2011-07-12 Spansion Llc Thin oxide dummy tiling as charge protection
US20080237751A1 (en) * 2007-03-30 2008-10-02 Uday Shah CMOS Structure and method of manufacturing same
JP5248063B2 (ja) * 2007-08-30 2013-07-31 株式会社日立ハイテクノロジーズ 半導体素子加工方法
US8012811B2 (en) * 2008-01-03 2011-09-06 International Business Machines Corporation Methods of forming features in integrated circuits
US8168542B2 (en) * 2008-01-03 2012-05-01 International Business Machines Corporation Methods of forming tubular objects
JP5579374B2 (ja) * 2008-07-16 2014-08-27 株式会社日立ハイテクノロジーズ 半導体加工方法
JP5042162B2 (ja) * 2008-08-12 2012-10-03 株式会社日立ハイテクノロジーズ 半導体加工方法
JP5210915B2 (ja) * 2009-02-09 2013-06-12 株式会社東芝 半導体装置の製造方法
JP5250476B2 (ja) * 2009-05-11 2013-07-31 株式会社日立ハイテクノロジーズ ドライエッチング方法
KR20110042614A (ko) * 2009-10-19 2011-04-27 삼성전자주식회사 반도체 소자 및 그 형성방법
US10438909B2 (en) 2016-02-12 2019-10-08 Globalfoundries Singapore Pte. Ltd. Reliable passivation for integrated circuits
US10685849B1 (en) 2019-05-01 2020-06-16 Applied Materials, Inc. Damage free metal conductor formation
CN115954271A (zh) * 2023-02-17 2023-04-11 安徽光智科技有限公司 金属层-介质层复合膜层的刻蚀方法
CN118888452A (zh) * 2024-07-05 2024-11-01 珠海格力电子元器件有限公司 一种半导体结构的制备方法和半导体器件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5948703A (en) 1998-06-08 1999-09-07 Advanced Micro Devices, Inc. Method of soft-landing gate etching to prevent gate oxide damage
US6492277B1 (en) * 1999-09-10 2002-12-10 Hitachi, Ltd. Specimen surface processing method and apparatus
JP3705977B2 (ja) * 1999-12-03 2005-10-12 松下電器産業株式会社 ゲート電極の形成方法
US6794229B2 (en) * 2000-04-28 2004-09-21 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for semiconductor device
US6423644B1 (en) * 2000-07-12 2002-07-23 Applied Materials, Inc. Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures
JP3760843B2 (ja) * 2001-11-16 2006-03-29 三菱電機株式会社 半導体装置の製造方法
US6933243B2 (en) 2002-02-06 2005-08-23 Applied Materials, Inc. High selectivity and residue free process for metal on thin dielectric gate etch application
JP3646718B2 (ja) * 2002-10-04 2005-05-11 セイコーエプソン株式会社 半導体装置の製造方法
JP2005285809A (ja) * 2004-03-26 2005-10-13 Sony Corp 半導体装置およびその製造方法

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