JP2002535847A5 - - Google Patents

Download PDF

Info

Publication number
JP2002535847A5
JP2002535847A5 JP2000595374A JP2000595374A JP2002535847A5 JP 2002535847 A5 JP2002535847 A5 JP 2002535847A5 JP 2000595374 A JP2000595374 A JP 2000595374A JP 2000595374 A JP2000595374 A JP 2000595374A JP 2002535847 A5 JP2002535847 A5 JP 2002535847A5
Authority
JP
Japan
Prior art keywords
metal layer
layer
forming
etching
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000595374A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002535847A (ja
Filing date
Publication date
Priority claimed from US09/236,025 external-priority patent/US6159863A/en
Application filed filed Critical
Publication of JP2002535847A publication Critical patent/JP2002535847A/ja
Publication of JP2002535847A5 publication Critical patent/JP2002535847A5/ja
Pending legal-status Critical Current

Links

JP2000595374A 1999-01-22 2000-01-21 単一のエッチャ中でハードマスクおよび金属層をインサイチューエッチングする方法 Pending JP2002535847A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/236,025 US6159863A (en) 1999-01-22 1999-01-22 Insitu hardmask and metal etch in a single etcher
US09/236,025 1999-01-22
PCT/US2000/001503 WO2000044037A1 (en) 1999-01-22 2000-01-21 Method of in-situ etching a hard mask and a metal layer in a single etcher

Publications (2)

Publication Number Publication Date
JP2002535847A JP2002535847A (ja) 2002-10-22
JP2002535847A5 true JP2002535847A5 (https=) 2007-01-18

Family

ID=22887811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000595374A Pending JP2002535847A (ja) 1999-01-22 2000-01-21 単一のエッチャ中でハードマスクおよび金属層をインサイチューエッチングする方法

Country Status (5)

Country Link
US (1) US6159863A (https=)
EP (1) EP1166344A1 (https=)
JP (1) JP2002535847A (https=)
KR (1) KR100708422B1 (https=)
WO (1) WO2000044037A1 (https=)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420099B1 (en) * 1999-08-02 2002-07-16 Infineon Technologies Ag Tungsten hard mask for dry etching aluminum-containing layers
US6387820B1 (en) * 2000-09-19 2002-05-14 Advanced Micro Devices, Inc. BC13/AR chemistry for metal overetching on a high density plasma etcher
US6656643B2 (en) 2001-02-20 2003-12-02 Chartered Semiconductor Manufacturing Ltd. Method of extreme ultraviolet mask engineering
EP1235265A1 (en) * 2001-02-23 2002-08-28 Infineon Technologies AG Method for etching a hardmask layer and a metal layer
US6582861B2 (en) * 2001-03-16 2003-06-24 Applied Materials, Inc. Method of reshaping a patterned organic photoresist surface
US6573189B1 (en) 2001-11-07 2003-06-03 Taiwan Semiconductor Manufacturing Company Manufacture method of metal bottom ARC
US6861177B2 (en) * 2002-02-21 2005-03-01 Hitachi Global Storage Technologies Netherlands B.V. Method of forming a read sensor using a lift-off mask having a hardmask layer and a release layer
US6815367B2 (en) 2002-04-03 2004-11-09 Infineon Technologies Ag Elimination of resist footing on tera hardmask
DE10219122B4 (de) * 2002-04-29 2005-01-05 Infineon Technologies Ag Verfahren zur Herstellung von Hartmasken
DE10312469A1 (de) * 2003-03-20 2004-10-07 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterstruktur
US20040192059A1 (en) * 2003-03-28 2004-09-30 Mosel Vitelic, Inc. Method for etching a titanium-containing layer prior to etching an aluminum layer in a metal stack
KR100549272B1 (ko) * 2003-04-08 2006-02-03 동부아남반도체 주식회사 미세선폭을 갖는 반도체 소자의 제조 방법
KR100548515B1 (ko) * 2003-07-09 2006-02-02 매그나칩 반도체 유한회사 반도체 소자의 금속 배선의 형성 방법
US6972255B2 (en) * 2003-07-28 2005-12-06 Freescale Semiconductor, Inc. Semiconductor device having an organic anti-reflective coating (ARC) and method therefor
US7030008B2 (en) * 2003-09-12 2006-04-18 International Business Machines Corporation Techniques for patterning features in semiconductor devices
KR20050034887A (ko) * 2003-10-10 2005-04-15 삼성전자주식회사 전원전압 동기신호 생성 장치 및 방법
US20070037100A1 (en) * 2005-08-09 2007-02-15 International Business Machines Corporation High aspect ratio mask open without hardmask
US7972957B2 (en) * 2006-02-27 2011-07-05 Taiwan Semiconductor Manufacturing Company Method of making openings in a layer of a semiconductor device
US7435681B2 (en) * 2006-05-09 2008-10-14 Macronix International Co., Ltd. Methods of etching stacks having metal layers and hard mask layers
KR100785036B1 (ko) * 2006-12-12 2007-12-11 삼성전자주식회사 전기장 쉴드를 구비한 전기장 센서의 제조방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03156927A (ja) * 1989-10-24 1991-07-04 Hewlett Packard Co <Hp> アルミ・メタライゼーションのパターン形成方法
TW290717B (en) * 1994-10-28 1996-11-11 Advanced Micro Devices Inc Method to prevent formation of defects during multilayer interconnect processing
JPH0982687A (ja) * 1995-09-19 1997-03-28 Mitsubishi Electric Corp 半導体装置の製造方法
US5772906A (en) * 1996-05-30 1998-06-30 Lam Research Corporation Mechanism for uniform etching by minimizing effects of etch rate loading
US5772903A (en) * 1996-09-27 1998-06-30 Hirsch; Gregory Tapered capillary optics
US5851926A (en) * 1996-10-01 1998-12-22 Applied Materials, Inc Method for etching transistor gates using a hardmask
US6013582A (en) * 1997-12-08 2000-01-11 Applied Materials, Inc. Method for etching silicon oxynitride and inorganic antireflection coatings
US5981398A (en) * 1998-04-10 1999-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Hard mask method for forming chlorine containing plasma etched layer
US6017826A (en) * 1998-10-05 2000-01-25 Chartered Semiconductor Manufacturing, Ltd. Chlorine containing plasma etch method with enhanced sidewall passivation and attenuated microloading effect

Similar Documents

Publication Publication Date Title
JP2002535847A5 (https=)
US6255022B1 (en) Dry development process for a bi-layer resist system utilized to reduce microloading
US6750127B1 (en) Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance
TW200834660A (en) Methods to reduce the critical dimension of semiconductor devices and partially fabricated semiconductor devices having reduced critical dimensions
US20060084243A1 (en) Oxidation sidewall image transfer patterning method
JP2002280388A (ja) 半導体装置の製造方法
US6362093B1 (en) Dual damascene method employing sacrificial via fill layer
US20110254142A1 (en) Stacked structure
US6797552B1 (en) Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices
EP0859400A3 (en) Improvements in or relating to integrated circuits
US6667222B1 (en) Method to combine zero-etch and STI-etch processes into one process
CN110690112B (zh) 利用反向间距加倍工艺形成表面平坦化结构及方法
TW200532800A (en) Method for fabricating a hard mask polysilicon gate
JP3906037B2 (ja) 半導体装置の製造方法
US7538025B2 (en) Dual damascene process flow for porous low-k materials
JP3585039B2 (ja) ホール形成方法
WO2002043140A3 (en) Imaging layer as hard mask for organic low-k materials
KR100632422B1 (ko) 반도체 기판내에 구조를 형성하는 방법
JP2003158179A (ja) 半導体装置およびその製造方法
US6812077B1 (en) Method for patterning narrow gate lines
KR100816210B1 (ko) 반도체 장치 형성 방법
CN101136333A (zh) 堆栈结构以及以此堆栈结构图案化的方法
JP2000260871A (ja) 半導体装置の製造方法
KR100333378B1 (ko) 반도체 소자의 제조방법
JP3877461B2 (ja) 半導体装置の製造方法