JP2002535847A - 単一のエッチャ中でハードマスクおよび金属層をインサイチューエッチングする方法 - Google Patents

単一のエッチャ中でハードマスクおよび金属層をインサイチューエッチングする方法

Info

Publication number
JP2002535847A
JP2002535847A JP2000595374A JP2000595374A JP2002535847A JP 2002535847 A JP2002535847 A JP 2002535847A JP 2000595374 A JP2000595374 A JP 2000595374A JP 2000595374 A JP2000595374 A JP 2000595374A JP 2002535847 A JP2002535847 A JP 2002535847A
Authority
JP
Japan
Prior art keywords
layer
hard mask
metal layer
mask material
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000595374A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002535847A5 (https=
Inventor
チェン，スーザン
リズートウ，ジュディ・クアン
サンダーファ，アン・イー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2002535847A publication Critical patent/JP2002535847A/ja
Publication of JP2002535847A5 publication Critical patent/JP2002535847A5/ja
Pending legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H10P76/2043—Photolithographic processes using an anti-reflective coating

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP2000595374A 1999-01-22 2000-01-21 単一のエッチャ中でハードマスクおよび金属層をインサイチューエッチングする方法 Pending JP2002535847A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/236,025 US6159863A (en) 1999-01-22 1999-01-22 Insitu hardmask and metal etch in a single etcher
US09/236,025 1999-01-22
PCT/US2000/001503 WO2000044037A1 (en) 1999-01-22 2000-01-21 Method of in-situ etching a hard mask and a metal layer in a single etcher

Publications (2)

Publication Number Publication Date
JP2002535847A true JP2002535847A (ja) 2002-10-22
JP2002535847A5 JP2002535847A5 (https=) 2007-01-18

Family

ID=22887811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000595374A Pending JP2002535847A (ja) 1999-01-22 2000-01-21 単一のエッチャ中でハードマスクおよび金属層をインサイチューエッチングする方法

Country Status (5)

Country Link
US (1) US6159863A (https=)
EP (1) EP1166344A1 (https=)
JP (1) JP2002535847A (https=)
KR (1) KR100708422B1 (https=)
WO (1) WO2000044037A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007500443A (ja) * 2003-07-28 2007-01-11 フリースケール セミコンダクター インコーポレイテッド 有機反射防止膜（ａｒｃ）を有する半導体装置及びその方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420099B1 (en) * 1999-08-02 2002-07-16 Infineon Technologies Ag Tungsten hard mask for dry etching aluminum-containing layers
US6387820B1 (en) * 2000-09-19 2002-05-14 Advanced Micro Devices, Inc. BC13/AR chemistry for metal overetching on a high density plasma etcher
US6656643B2 (en) 2001-02-20 2003-12-02 Chartered Semiconductor Manufacturing Ltd. Method of extreme ultraviolet mask engineering
EP1235265A1 (en) * 2001-02-23 2002-08-28 Infineon Technologies AG Method for etching a hardmask layer and a metal layer
US6582861B2 (en) * 2001-03-16 2003-06-24 Applied Materials, Inc. Method of reshaping a patterned organic photoresist surface
US6573189B1 (en) 2001-11-07 2003-06-03 Taiwan Semiconductor Manufacturing Company Manufacture method of metal bottom ARC
US6861177B2 (en) * 2002-02-21 2005-03-01 Hitachi Global Storage Technologies Netherlands B.V. Method of forming a read sensor using a lift-off mask having a hardmask layer and a release layer
US6815367B2 (en) 2002-04-03 2004-11-09 Infineon Technologies Ag Elimination of resist footing on tera hardmask
DE10219122B4 (de) * 2002-04-29 2005-01-05 Infineon Technologies Ag Verfahren zur Herstellung von Hartmasken
DE10312469A1 (de) * 2003-03-20 2004-10-07 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterstruktur
US20040192059A1 (en) * 2003-03-28 2004-09-30 Mosel Vitelic, Inc. Method for etching a titanium-containing layer prior to etching an aluminum layer in a metal stack
KR100549272B1 (ko) * 2003-04-08 2006-02-03 동부아남반도체 주식회사 미세선폭을 갖는 반도체 소자의 제조 방법
KR100548515B1 (ko) * 2003-07-09 2006-02-02 매그나칩 반도체 유한회사 반도체 소자의 금속 배선의 형성 방법
US7030008B2 (en) * 2003-09-12 2006-04-18 International Business Machines Corporation Techniques for patterning features in semiconductor devices
KR20050034887A (ko) * 2003-10-10 2005-04-15 삼성전자주식회사 전원전압 동기신호 생성 장치 및 방법
US20070037100A1 (en) * 2005-08-09 2007-02-15 International Business Machines Corporation High aspect ratio mask open without hardmask
US7972957B2 (en) * 2006-02-27 2011-07-05 Taiwan Semiconductor Manufacturing Company Method of making openings in a layer of a semiconductor device
US7435681B2 (en) * 2006-05-09 2008-10-14 Macronix International Co., Ltd. Methods of etching stacks having metal layers and hard mask layers
KR100785036B1 (ko) * 2006-12-12 2007-12-11 삼성전자주식회사 전기장 쉴드를 구비한 전기장 센서의 제조방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03156927A (ja) * 1989-10-24 1991-07-04 Hewlett Packard Co <Hp> アルミ・メタライゼーションのパターン形成方法
TW290717B (en) * 1994-10-28 1996-11-11 Advanced Micro Devices Inc Method to prevent formation of defects during multilayer interconnect processing
JPH0982687A (ja) * 1995-09-19 1997-03-28 Mitsubishi Electric Corp 半導体装置の製造方法
US5772906A (en) * 1996-05-30 1998-06-30 Lam Research Corporation Mechanism for uniform etching by minimizing effects of etch rate loading
US5772903A (en) * 1996-09-27 1998-06-30 Hirsch; Gregory Tapered capillary optics
US5851926A (en) * 1996-10-01 1998-12-22 Applied Materials, Inc Method for etching transistor gates using a hardmask
US6013582A (en) * 1997-12-08 2000-01-11 Applied Materials, Inc. Method for etching silicon oxynitride and inorganic antireflection coatings
US5981398A (en) * 1998-04-10 1999-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Hard mask method for forming chlorine containing plasma etched layer
US6017826A (en) * 1998-10-05 2000-01-25 Chartered Semiconductor Manufacturing, Ltd. Chlorine containing plasma etch method with enhanced sidewall passivation and attenuated microloading effect

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007500443A (ja) * 2003-07-28 2007-01-11 フリースケール セミコンダクター インコーポレイテッド 有機反射防止膜（ａｒｃ）を有する半導体装置及びその方法
US8039389B2 (en) 2003-07-28 2011-10-18 Freescale Semiconductor, Inc. Semiconductor device having an organic anti-reflective coating (ARC) and method therefor

Also Published As

Publication number Publication date
KR100708422B1 (ko) 2007-04-18
US6159863A (en) 2000-12-12
KR20010101641A (ko) 2001-11-14
EP1166344A1 (en) 2002-01-02
WO2000044037A1 (en) 2000-07-27

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