KR20070057844A - 금속층을 갖는 반도체 디바이스를 형성하는 방법 - Google Patents

금속층을 갖는 반도체 디바이스를 형성하는 방법 Download PDF

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Publication number
KR20070057844A
KR20070057844A KR1020077006284A KR20077006284A KR20070057844A KR 20070057844 A KR20070057844 A KR 20070057844A KR 1020077006284 A KR1020077006284 A KR 1020077006284A KR 20077006284 A KR20077006284 A KR 20077006284A KR 20070057844 A KR20070057844 A KR 20070057844A
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KR
South Korea
Prior art keywords
metal layer
chemistry
etch
etching
metal
Prior art date
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KR1020077006284A
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English (en)
Korean (ko)
Inventor
탭 에이. 스티븐스
브라이언 제이. 굴스비
비츠-옌 규엔
분-예 틴
Original Assignee
프리스케일 세미컨덕터, 인크.
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Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20070057844A publication Critical patent/KR20070057844A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/963—Removing process residues from vertical substrate surfaces

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  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020077006284A 2004-09-17 2005-08-23 금속층을 갖는 반도체 디바이스를 형성하는 방법 Withdrawn KR20070057844A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/943,383 US7208424B2 (en) 2004-09-17 2004-09-17 Method of forming a semiconductor device having a metal layer
US10/943,383 2004-09-17

Publications (1)

Publication Number Publication Date
KR20070057844A true KR20070057844A (ko) 2007-06-07

Family

ID=36074612

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020077006284A Withdrawn KR20070057844A (ko) 2004-09-17 2005-08-23 금속층을 갖는 반도체 디바이스를 형성하는 방법

Country Status (4)

Country Link
US (1) US7208424B2 (https=)
JP (1) JP4891906B2 (https=)
KR (1) KR20070057844A (https=)
WO (1) WO2006033746A2 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7354847B2 (en) * 2004-01-26 2008-04-08 Taiwan Semiconductor Manufacturing Company Method of trimming technology
KR100562657B1 (ko) * 2004-12-29 2006-03-20 주식회사 하이닉스반도체 리세스게이트 및 그를 구비한 반도체장치의 제조 방법
US7435681B2 (en) * 2006-05-09 2008-10-14 Macronix International Co., Ltd. Methods of etching stacks having metal layers and hard mask layers
JP5578389B2 (ja) * 2006-05-16 2014-08-27 Ｎｌｔテクノロジー株式会社 積層膜パターン形成方法及びゲート電極形成方法
US7655550B2 (en) * 2006-06-30 2010-02-02 Freescale Semiconductor, Inc. Method of making metal gate transistors
US8394724B2 (en) * 2006-08-31 2013-03-12 Globalfoundries Singapore Pte. Ltd. Processing with reduced line end shortening ratio
US7977218B2 (en) * 2006-12-26 2011-07-12 Spansion Llc Thin oxide dummy tiling as charge protection
US20080237751A1 (en) * 2007-03-30 2008-10-02 Uday Shah CMOS Structure and method of manufacturing same
JP5248063B2 (ja) * 2007-08-30 2013-07-31 株式会社日立ハイテクノロジーズ 半導体素子加工方法
US8012811B2 (en) * 2008-01-03 2011-09-06 International Business Machines Corporation Methods of forming features in integrated circuits
US8168542B2 (en) * 2008-01-03 2012-05-01 International Business Machines Corporation Methods of forming tubular objects
JP5579374B2 (ja) * 2008-07-16 2014-08-27 株式会社日立ハイテクノロジーズ 半導体加工方法
JP5042162B2 (ja) * 2008-08-12 2012-10-03 株式会社日立ハイテクノロジーズ 半導体加工方法
JP5210915B2 (ja) * 2009-02-09 2013-06-12 株式会社東芝 半導体装置の製造方法
JP5250476B2 (ja) * 2009-05-11 2013-07-31 株式会社日立ハイテクノロジーズ ドライエッチング方法
KR20110042614A (ko) * 2009-10-19 2011-04-27 삼성전자주식회사 반도체 소자 및 그 형성방법
US10438909B2 (en) 2016-02-12 2019-10-08 Globalfoundries Singapore Pte. Ltd. Reliable passivation for integrated circuits
US10685849B1 (en) 2019-05-01 2020-06-16 Applied Materials, Inc. Damage free metal conductor formation
CN115954271A (zh) * 2023-02-17 2023-04-11 安徽光智科技有限公司 金属层-介质层复合膜层的刻蚀方法
CN118888452A (zh) * 2024-07-05 2024-11-01 珠海格力电子元器件有限公司 一种半导体结构的制备方法和半导体器件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5948703A (en) 1998-06-08 1999-09-07 Advanced Micro Devices, Inc. Method of soft-landing gate etching to prevent gate oxide damage
US6492277B1 (en) * 1999-09-10 2002-12-10 Hitachi, Ltd. Specimen surface processing method and apparatus
JP3705977B2 (ja) * 1999-12-03 2005-10-12 松下電器産業株式会社 ゲート電極の形成方法
US6794229B2 (en) * 2000-04-28 2004-09-21 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for semiconductor device
US6423644B1 (en) * 2000-07-12 2002-07-23 Applied Materials, Inc. Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures
JP3760843B2 (ja) * 2001-11-16 2006-03-29 三菱電機株式会社 半導体装置の製造方法
US6933243B2 (en) 2002-02-06 2005-08-23 Applied Materials, Inc. High selectivity and residue free process for metal on thin dielectric gate etch application
JP3646718B2 (ja) * 2002-10-04 2005-05-11 セイコーエプソン株式会社 半導体装置の製造方法
JP2005285809A (ja) * 2004-03-26 2005-10-13 Sony Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP2008514001A (ja) 2008-05-01
JP4891906B2 (ja) 2012-03-07
US20060063364A1 (en) 2006-03-23
US7208424B2 (en) 2007-04-24
WO2006033746A3 (en) 2007-05-10
WO2006033746A2 (en) 2006-03-30

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