TWI471904B - 在製造一半導體裝置期間使用之方法、用於形成非對稱半導體裝置特徵之方法及包括該半導體裝置之結構 - Google Patents
在製造一半導體裝置期間使用之方法、用於形成非對稱半導體裝置特徵之方法及包括該半導體裝置之結構 Download PDFInfo
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Description
本發明的各種實施例涉及半導體製造的領域。更具體地說,本發明的實施例揭露了一種用於使用對稱光罩來選擇性地形成對稱或非對稱特徵的方法。
在半導體裝置的形成期間,很多特徵,比如導電線、接觸、介電隔離及其他特徵,通常被形成在一半導體晶圓上或其中。半導體裝置的工程師的一個目標是形成儘可能多的這些特徵在一給定區域中以增加產量,降低製造成本以及最小化裝置。這些結構的形成通常需要使用微影技術。光學微影技術,大多數使用在領先的晶圓處理的該微影方法包括投射給定波長的相干光,通常248奈米(nm)或193 nm,從一照明源(照明燈)穿過一石英光罩或具有一代表特徵待形成的鍍鉻圖案的主光罩,並且成像該圖案到用光阻塗布的晶圓上。該光化學上改變該光阻並且使該曝光的光阻(如果正性光阻被使用)或該未曝光的光阻(如果負性光阻被使用)能夠使用顯影劑漂洗乾淨。
半導體裝置處理通常需要形成具有統一尺寸的對稱特徵,以及具有不同尺寸的非對稱特徵。為了形成對稱特徵,具有一規則鍍鉻圖案的一主光罩被用於曝光該光阻。非對稱特徵,具有兩個(或更多)不同形狀及/或電性質的特徵,其形成通常需要使用兩個(或更多)主光罩,其中一個主光罩定義每個特徵的圖案。
由於在半導體裝置製造中使用的典型的主光罩的複雜性,主光罩的製造是耗時的且昂貴的。需要一種微影方法,其使用一單一主光罩提供選擇性地形成對稱特徵或非對稱特徵。
術語"晶圓"應理解為一包含矽、矽絕緣體(SOI)或矽藍寶石技術(SOS)技術的基於半導體的材料,摻雜及未摻雜的半導體,由一基本半導體基板支撐的矽的磊晶層以及其他半導體結構。此外,當在以下描述中提及一"晶圓"時,可能已經利用先前的處理步驟在該基本半導體結構或基板中或之上形成區域或接面。另外,當在以下描述中提及一"基板總成"時,該基板總成可能取決於處理的具體階段包含一具有包含以下項目之材料的晶圓:介電與導體以及比如在其上形成之電晶體的特徵。另外,該半導體不需要是基於矽的,而是可能基於矽鍺、矽絕緣體、矽藍寶石、鍺或砷化鎵等等。此外,在本文討論及請求項中,使用相對於兩種材料的術語"在…上",一個在另一個之"上",意味著在該等材料之間至少有某個接觸,而"在…之上"意味著該等材料是非常接近的,但是有可能由於一或多個額外的介入材料使得接觸是有可能的但是不一定的。"在…上"及"在…之上"均不意味著這裏所使用的任何方向性。術語"等形的"描述一塗層材料,其中該基材材料的角度由該等形材料維持。術語"大約"表明列出的該值可能會改變,只要該改變不會導致不符合根據本發明的該說明實施例的要
求的該製程或結構。一"間隔物"表明一材料,通常是介電,作為一等形材料形成在不均勻位置之上,然後各向異性蝕刻以移除該材料的水平部分及留下該材料的縱向部分。
本發明的一實施例使用一具有一規則特徵圖案的單一主光罩提供選擇性地形成對稱特徵或非對稱特徵。一導致形成一非對稱特徵圖案的製程由圖1-8描繪,以及一導致形成一對稱特徵圖案的製程由圖1、2與9-13描繪。
圖1描繪一半導體晶圓基板總成的一部分,包括大約750埃()厚的多晶矽10;大約900厚的矽化鎢(WSix
)12;大約1,400厚的矽酸乙酯(TEOS)14;大約2,000厚的透明碳(TC)16;從大約200到大約360厚的介電抗反射塗層(DARC)18;具有水平寬度從大約40到大約70,縱向高度從大約1,200到大約2,000的統一尺寸的光阻20,其中該等光阻特徵具有一從大約170到大約200的規則間距(即,在鄰近光阻特徵的類似點之間的統一距離);以及等形間隔物材料22,例如包括從大約300到大約500厚的氮化矽(Si3
N4
)。個別地,這些材料的各個及其形成在該技術中是熟知的。該光阻提供一第一光罩材料,其將被用於定義間隔物,以及該間隔物材料將提供一第二光罩,其將被用於定義該基材材料。
從以下描述將明白,取決於本發明的使用,對於各個材料可使用除具體指定之材料以外的其他材料。在此實施例中,圖1中描繪的幾種材料可用於形成一NAND快閃記憶體
裝置。在另一實施例中,材料10-18的各者可由一單一介電材料(比如硼磷矽玻璃(BPSG))予以取代以形成另一類型裝置,或者以形成一NAND快閃記憶體裝置上的其他特徵。此外,如果使用所描繪的材料,則厚度可在超過上一段落中列出的該等值的一很廣的範圍上改變,但是這些材料以及厚度在用當前技術形成NAND快閃記憶體裝置期間被相信是足夠使用的。然而該DARC材料的厚度變化可由微影約束所限制,並且光阻中的任何變化及間隔物寬度可由特徵間距限制。
圖1的該等形間隔物材料22係使用垂直各向異性蝕刻予以蝕刻以形成複數個間隔物22,如圖2中所描繪。此蝕刻對圖案化材料20及DARC材料18有選擇性地移除間隔物材料(即,將移除間隔物材料22,並最小化圖案化材料20及DARC 18的蝕刻)。圖2描繪接觸每個光罩特徵20的成對截面間隔物。
在如圖2中所描繪的蝕刻間隔物22之後,使用各向異性蝕刻對圖案化材料20及間隔物22有選擇性地蝕刻DARC 18,其有一些各向同性性質以產生圖3的結構。這蝕刻將最好停止在TC 16上或其中,以及可包括以一從大約60 sccm到大約160 sccm的流速的四氟甲烷(CF4
),以一從大約5 sccm到大約60 sccm的流速的二氟甲烷(CH2
F2
),以及以一大約100 sccm流速的三氟甲烷(CHF3
)。在蝕刻期間,腔室壓力可能維持在大約5密爾陶爾與大約20密爾陶爾之間,並且電力範圍在大約600瓦特到大約1,200瓦特。雖然
在該間隔物下可發生一些介電底切(undercut),但是底切最好被減至最低。此蝕刻形成一或多個傾斜凹口在DARC 18中,其係起因於該等間隔物22的傾斜、鄰近間隔物的間距與該蝕刻的品質。在一實施例中,該傾斜凹口將有一從大約200到大約360的深度。
在如圖3中所描繪的蝕刻該傾斜凹口之後,使用任何適當的蝕刻對間隔物22、DARC 18以及任何曝露的TC 16有選擇地移除該圖案化材料20,以產生圖4中的結構。一較佳的蝕刻包括以一大約120 sccm的流速的二氧化硫(SO2
)與以一大約80 sccm的流速的氧氣(O2
)的混合物。此蝕刻可包括使用大約800瓦特的電力、8 mT的壓力與400 V的偏壓電壓。另一個充分的蝕刻將包括使用溴化氫(HBr)、O2
及對蝕刻為最佳的氮氣(N2
)。位置40描繪了間隔物22之間的開口,其中該圖案化材料20已經被移除以曝露DARC 18。經曝露DARC 18之這些區域有一水平輪廓。位置42描繪了間隔物22之間DARC 18內的該等傾斜凹口。曝露DARC 18的區域42有一比該等曝露的水平部分40更垂直定向的輪廓,其中圖案化材料20已經被移除。
隨後,DARC 18、TC 16、TEOS 14與WSix
12使用垂直各向異性蝕刻被蝕刻,其對於間隔物22是選擇性的且其停止在多晶矽10上或其中以形成圖5的結構。各種已知的蝕刻可被用於移除這些材料的各個以轉移初始圖案到這些底層。如圖5中所描繪,一較小體積的材料已經被從材料12-18移除以形成開口42而不是形成開口40。該等描繪的材料
的位置40比位置42蝕刻更快,其可能由於該蝕刻劑的較高的衝擊能量,因為它接觸在位置40的該等各種材料的水平底部,而該蝕刻劑可由在位置42的間隔物22的傾斜側壁偏轉。因此圖5描繪了區域40,其有一矩形輪廓,其比有一"V"形輪廓的區域42蝕刻更深。
在形成圖5的結構之後,可對於該等曝露材料有選擇性地移除間隔物22以形成圖6的結構。圖6描繪了在位置40的開口,其等相對於在位置42的開口是不對稱的。已使用如圖1中描繪的對稱圖案化材料20形成這些開口40、42,並且可起因於每個間隔物的兩個垂直定向側之間的傾斜差異。如圖4中所描繪,例如,實體接觸圖案化材料20的每個間隔物之側是線性的且一般為垂直的(即,有一垂直的或接近垂直的輪廓),而沒有接觸圖案化材料20的每個間隔物之側係更傾斜且有一更圓化的輪廓。
雖然各種持續的製程可能完成於圖6之結構,一種使用被描繪在圖7與8中。如圖7中所描繪,一毯覆性介電材料70及一毯覆性導電材料72可被形成在圖6結構的表面之上以填充在位置40與42的該等開口。接著,對材料70實行一平坦化製程(比如機械平坦化,例如,化學機械平坦化製程(CMP)),以形成圖8之結構。圖8描繪了具有一第一截面的導電特徵80及具有一不同於該第一截面的第二截面的特徵82。特徵80可能有與特徵82不同的電性質,特別是如果該等特徵沿著其長度一般是統一的。例如,由於較大的截面面積特徵82,特徵80的電阻可能低於特徵82。此外,該
兩個特徵80、82可能形成兩個不同的隔離線,特別是具有一摻雜基板及填充渠溝的氧化物或另一介電。
在本發明的另一實施例中,使用用於形成圖1的該圖案化材料20的相同主光罩的對稱特徵被描繪在圖1、2與9-13中。在該實施例中,圖1與2的該等結構按照上述的該實施例被形成。
在形成圖2的結構之後,對於DARC 18及間隔物22有選擇性地移除圖案化材料20以形成圖9的結構。接著,使用各向同性蝕刻對間隔物22有選擇性地蝕刻DARC 18、TC 16、TEOS 14及WSix
12以形成圖10的結構。該DARC可能使用各向同性蝕刻,比如CF4
/CH2
F2
蝕刻,其中該CF4
:CH2
F2
比例至少是4。TC可能用先前實施例所討論的SO2
/O2
予以蝕刻。可用以一大約75 sccm的流速的CF4
及以一大約45 sccm的流速的O2
,5 mT的腔室壓力及1,500瓦特的電力以及300 V偏壓電壓來蝕刻TEOS。可用各以大約40 sccm的流速的三氟化氮(NF3
)及氯氣(Cl2
),大約15 mT的腔室壓力,大約400瓦特的電力及大約150 V偏壓電壓蝕刻矽化鎢,但可使用其他蝕刻製程。
隨後,對該等曝露材料有選擇性地移除間隔物22以形成圖11結構,其描繪了蝕刻入DARC 18、TC 16、TEOS 14與WSix
12的對稱開口110。這些對稱開口使用圖2的該圖案化材料20形成,其被用於形成該先前實施例的該等非對稱開口。因此無論是對稱或非對稱特徵可使用該相同對稱圖案形成。
如對於該先前實施例,圖11的結構可能有各種功能。一種這樣的功能被描繪在圖12與13中。在圖12中,一毯覆性介電120及一毯覆性導電材料122已經被形成在圖11的結構之上且在開口110內。介電120及導電材料122然後可使用機械平坦化(比如CMP)被平坦化,以形成圖13的結構。這些特徵可用作導電線或可能有其他用途。如圖13中所描繪,每個導電特徵122有類似的截面及電性質,其由於製程差異可能有所不同。
取決於本發明的該等實施例的實際使用,圖8與13所表示的該等實際結構可能有其他特徵,其等不是直接與該等製程及結構有關係,並且其等為了簡單解釋沒有被描述或描繪。該等製程及結構的各種使用是有可能的,比如使用於垂直電晶體或電容器、硬罩、淺溝槽隔離以及在該陣列及周圍中的其他裝置特徵。
如圖14中所描繪,按照本發明的一實施例形成的一半導體裝置140可連同其他裝置,比如一微處理器142,被附加到一印刷電路板144,例如附加到一電腦主板或作為用在個人電腦、小型電腦或主機146中的記憶體模組的一部分。圖14也可代表裝置140使用在包括一外殼146的其他電子裝置中,例如裝置包括一微處理器142,涉及電信、汽車工業、半導體測試及製造設備、消費類電子或幾乎任何一個消費類或工業電子設備。
這裏描述的該製程及結構能被用於製造很多不同結構,包括根據本發明製程形成的一金屬材料,以產生一緻密的
金屬材料,相比於傳統材料具有降低的電阻及減少的污染。圖15,例如是一裝置的簡化框圖,比如一動態隨機存取記憶體,其可能包括導電互連及其他特徵,其等可使用本發明的一實施例形成。這樣的一種裝置的一般操作對於熟習此項技術者是眾所周知的。圖15描繪了耦合到一記憶體裝置140的一處理器142,並且進一步描繪了一記憶體積體電路的以下基本部分:控制電路150;列位址緩衝器152及行位址緩衝器154;列解碼器156與行解碼器158;感測放大器160;記憶體陣列162;以及資料輸入/輸出164。
雖然本發明已經參考說明性的實施例被描述,但是這描述並不意為被視為限制意識。該等說明性的實施例的各種修飾,以及本發明的額外實施例對於熟習此項技術者在參考該描述之後將是顯而易見的。因此希望該等所附請求項將涵蓋任何屬於本發明實質範圍內的這樣的修飾或實施例。
10‧‧‧多晶矽
12‧‧‧矽化鎢
14‧‧‧矽酸乙酯
16‧‧‧透明碳
18‧‧‧介電抗反射塗層
20‧‧‧光阻/圖案化材料
22‧‧‧等形間隔物材料
40‧‧‧開口
42‧‧‧開口
70‧‧‧毯覆性介電材料
72‧‧‧毯覆性導電材料
80‧‧‧導電特徵
82‧‧‧導電特徵
120‧‧‧毯覆性介電材料
122‧‧‧毯覆性導電材料
140‧‧‧記憶體裝置
142‧‧‧處理器
144‧‧‧印刷電路板
146‧‧‧主機
150‧‧‧控制電路
152‧‧‧列位址緩衝器
154‧‧‧行位址緩衝器
156‧‧‧列解碼器
158‧‧‧行解碼器
160‧‧‧感測放大器
162‧‧‧記憶體陣列
164‧‧‧資料輸入/輸出
圖1-2是描繪本發明的各種實施例的最初結構的截面圖;圖3-8是描繪本發明的一第一實施例的截面圖;圖9-13是描繪本發明的一第二實施例的截面圖;圖14是各種元件的等角描繪,其等可能使用與本發明的一實施例形成的裝置被製造;以及圖15是本發明的一實施例的框圖,以形成一具有一儲存電晶體陣列的記憶體裝置的部分。
應強調,這裏的該等圖式可能不是按確切的比例且是示意圖。該等圖式並不意為描繪該等具體參數、材料、特殊用途或本發明的結構性細節,其可由熟習此項技術者經由檢查本文資訊確定。
140‧‧‧記憶體裝置
142‧‧‧處理器
150‧‧‧控制電路
152‧‧‧列位址緩衝器
154‧‧‧行位址緩衝器
156‧‧‧列解碼器
158‧‧‧行解碼器
160‧‧‧感測放大器
162‧‧‧記憶體陣列
164‧‧‧資料輸入/輸出
Claims (20)
- 一種在半導體裝置特徵製造期間使用之方法,其包括:形成待蝕刻的至少一材料;形成複數個第一光罩特徵於第一位置處及形成複數個第二光罩特徵於待蝕刻的該材料上;在第二位置處利用一第一蝕刻部分蝕刻入待蝕刻的該材料,以及在該等第一位置使待蝕刻的該材料保持未蝕刻;移除該等第一光罩特徵;然後在該等第二光罩特徵曝露的情況下,在該等第一位置與該等第二位置兩者處利用一第二蝕刻蝕刻待蝕刻的該材料。
- 如請求項1之方法,其中在第二位置處用該第一蝕刻蝕刻入待蝕刻的該材料之製程動作係在該等第一光罩特徵與該等第二光罩特徵兩者皆經曝露的情況下予以執行。
- 如請求項1之方法,進一步包括:在該第二蝕刻期間在該等第一位置處從待蝕刻的該材料蝕刻一第一體積的材料以形成第一開口;以及在該第一蝕刻與該第二蝕刻期間在該等第二位置從待蝕刻的該材料蝕刻一第二體積的材料以形成第二開口,其中該第二體積的材料不同於該第一體積的材料。
- 如請求項3之方法,其中蝕刻的該第二體積的材料少於蝕刻的該第一體積的材料。
- 如請求項4之方法,其進一步包括形成一導電材料以填 充該等第一與第二開口,其中該第一開口中之該導電材料的一第一截面面積不同於該第二開口中之該導電材料的一第二截面面積。
- 如請求項5之方法,其中該第二截面面積小於該第一截面面積。
- 一種在製造一半導體裝置期間使用之方法,其包括:形成複數個光罩特徵於待蝕刻的一材料之上,其中該複數個光罩特徵有統一尺寸及一規則間距;形成一等形間隔物材料於待蝕刻的該材料之上以及在該複數個光罩特徵上;蝕刻該等形間隔物材料以形成複數個間隔物,其中成對的間隔物接觸每個光罩特徵的至少一部分;在該複數個光罩特徵及該複數個間隔物曝露的情形下,部分蝕刻待蝕刻的該材料以在待蝕刻的該材料中形成複數個部分蝕刻之第一開口;移除該複數個光罩特徵以在該等成對間隔物之每一對之間形成一開口;然後在該複數個間隔物曝露的情形下,蝕刻待蝕刻的該材料穿過該等成對間隔物之每一對之間之該開口以在待蝕刻的該材料中形成第二開口,並且進一步蝕刻該等部分蝕刻之第一開口以形成完整的第一開口,其中該等第二開口包括一不同於該等完整的第一開口之截面輪廓。
- 如請求項7之方法,其進一步包括:在該等第二開口中及在該等完整的第一開口中形成一 導電材料;以及平坦化該導電材料以移除在待蝕刻的該材料之上之該導電材料,其中該等完整的第一開口內的一第一體積的導電材料少於該等第二開口內的一第二體積的導電材料。
- 如請求項7之方法,其進一步包括:形成該等第二開口以有一矩形輪廓;以及形成該等完整的第一開口以有一"V"形輪廓。
- 一種在製造一半導體裝置期間使用之方法,其包括:形成多晶矽在一半導體晶圓基板總成之上,該半導體晶圓基板總成包括一半導體晶圓之至少一部分;形成矽化物在該多晶矽上;形成氧化物在該矽化物上;形成透明碳(TC)在該氧化物上;形成介電抗反射塗層(DARC)在該TC上;形成複數個第一光罩特徵在第一位置及複數個第二光罩特徵在該DARC之上;在該等第一光罩特徵與該等第二光罩特徵曝露的情形下,使用各向同性蝕刻蝕刻該DARC以及當該TC被曝露時停止該蝕刻;移除該等第一光罩特徵;然後在該等第二光罩特徵曝露的情形下,在該第一位置蝕刻該TC並且停止在該氧化物上或其中以形成一第一開口,而在一第二位置蝕刻該DARC、該TC、該氧化物及 該矽化物並且停止在該多晶矽上或其中以形成一第二開口。
- 如請求項10之方法,其進一步包括:從該DARC及該TC蝕刻一第一體積的材料以形成該第一開口;以及從該DARC、該TC、該氧化物及該矽化物蝕刻一第二體積的材料以形成該第二開口,其中該第二體積大於該第一體積。
- 如請求項11之方法,其進一步包括形成一導電材料以填充該等第一與第二開口,其中該第一開口中之該導電材料的一第一截面面積小於該第二開口中之該導電材料的一第二截面面積。
- 如請求項11之方法,其中該半導體裝置是一NAND快閃記憶體裝置,以及該方法進一步包括:形成厚度750Å之該多晶矽;形成厚度900Å之該矽化物;形成厚度1,400Å之該氧化物;形成厚度2,000Å之該TC;以及形成厚度從200Å到360Å之該DARC。
- 一種用於形成非對稱半導體裝置特徵之方法,其包括:形成待蝕刻的一材料;形成一具有複數個對稱特徵之圖案化光罩於待蝕刻的該材料之上;形成一間隔物材料在該複數個對稱特徵之上; 在兩個截面間隔物接觸該複數個對稱特徵之至少一部分情況下,蝕刻該間隔物材料以形成複數個間隔物;在該等間隔物及該圖案化光罩曝露的情形下,在複數個第一位置蝕刻待蝕刻的該材料,而複數個第二位置維持不被蝕刻;移除該圖案化光罩;然後在該等間隔物曝露的情形下,在該複數個第一位置及在該複數個第二位置蝕刻待蝕刻的該材料以導致待蝕刻的該材料包括具有一第一截面輪廓之於該第一位置處的第一蝕刻特徵以及具有一不同於該第一截面之第二截面之於該第二位置的第二蝕刻特徵。
- 如請求項14之方法,其進一步包括使用一包括下列各者之方法形成待蝕刻的該材料:形成一矽化鎢材料;形成一矽酸乙酯玻璃材料在該矽化鎢材料上;形成一透明碳材料在該矽酸乙酯玻璃材料上;以及形成一介電抗反射塗層在該透明碳材料上。
- 如請求項15之方法,其進一步包括形成該矽化鎢材料在一多晶矽材料上。
- 如請求項14之方法,其進一步包括:形成一等形導電材料在該等第一蝕刻特徵內、在該等第二蝕刻特徵內以及在待蝕刻的該材料之上;以及移除在待蝕刻的該材料之上之該等形導電材料,其中在移除在待蝕刻的該材料之上之該等形導電材料後,該 等第一與第二蝕刻特徵仍然填充有導電材料。
- 一種結構,其包括:一待蝕刻的結構,其包括:一多晶矽材料;覆在該多晶矽材料上之一矽化鎢材料;覆在該矽化鎢材料上之一介電材料;覆在該介電材料上之一透明碳(TC)材料;及覆在該TC材料上之一抗反射材料;以及覆在該抗反射材料上之複數個成對的截面光罩材料間隔物。
- 如請求項18之結構,其進一步包括:該多晶矽材料750埃(Å)厚並且接觸該矽化鎢材料;該矽化鎢材料900Å厚並且接觸該介電材料;該介電材料是1400Å厚的矽酸乙酯(TEOS)材料並且接觸該TC材料;該透明碳層2,000Å厚並且接觸該抗反射材料;以及該抗反射材料是從200Å到260Å厚的一沈積抗反射塗層(DARC)。
- 如請求項19之結構,其進一步包括:在鄰近成對的間隔物之間及在鄰近的間隔物對之間具有統一間距之該複數個成對的截面光罩材料間隔物,其中鄰近成對的間隔物之間的該間距等於鄰近的間隔物對之間的該間距;在低於該複數個成對的截面光罩材料間隔物的一位階 處之複數個第一開口,其中一第一開口位於每個成對的間隔物之間;以及在低於該複數個成對的截面光罩材料間隔物的一位階處之複數個第二開口,其中一第二開口位於每個間隔物對之間,其中每個第一開口之體積實質上小於每個第二開口之體積。
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US11/766,931 US7985681B2 (en) | 2007-06-22 | 2007-06-22 | Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during fabrication of a semiconductor device and electronic systems including the semiconductor device |
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US9385132B2 (en) * | 2011-08-25 | 2016-07-05 | Micron Technology, Inc. | Arrays of recessed access devices, methods of forming recessed access gate constructions, and methods of forming isolation gate constructions in the fabrication of recessed access devices |
JP5899082B2 (ja) * | 2012-08-08 | 2016-04-06 | 富士フイルム株式会社 | パターン形成方法、及び、これを用いた電子デバイスの製造方法 |
US9093378B2 (en) * | 2013-03-15 | 2015-07-28 | Samsung Electronics Co., Ltd. | Method for forming patterns of semiconductor device using SADP process |
US9005463B2 (en) | 2013-05-29 | 2015-04-14 | Micron Technology, Inc. | Methods of forming a substrate opening |
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US20110248385A1 (en) | 2011-10-13 |
EP2160754A4 (en) | 2011-12-21 |
US7985681B2 (en) | 2011-07-26 |
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TW200917336A (en) | 2009-04-16 |
WO2009002389A3 (en) | 2009-02-19 |
JP5382464B2 (ja) | 2014-01-08 |
KR20100052462A (ko) | 2010-05-19 |
EP2160754A2 (en) | 2010-03-10 |
EP2160754B1 (en) | 2013-11-06 |
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