JP2008512920A5 - - Google Patents

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Publication number
JP2008512920A5
JP2008512920A5 JP2007530809A JP2007530809A JP2008512920A5 JP 2008512920 A5 JP2008512920 A5 JP 2008512920A5 JP 2007530809 A JP2007530809 A JP 2007530809A JP 2007530809 A JP2007530809 A JP 2007530809A JP 2008512920 A5 JP2008512920 A5 JP 2008512920A5
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JP
Japan
Prior art keywords
circuit
phase
locked loop
controlled oscillator
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007530809A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008512920A (ja
JP4815572B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/IB2005/052840 external-priority patent/WO2006030335A2/en
Publication of JP2008512920A publication Critical patent/JP2008512920A/ja
Publication of JP2008512920A5 publication Critical patent/JP2008512920A5/ja
Application granted granted Critical
Publication of JP4815572B2 publication Critical patent/JP4815572B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007530809A 2004-09-13 2005-08-30 補償された高速pll回路 Expired - Fee Related JP4815572B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP04104413.2 2004-09-13
EP04104413 2004-09-13
PCT/IB2005/052840 WO2006030335A2 (en) 2004-09-13 2005-08-30 Compensated high-speed pll circuit

Publications (3)

Publication Number Publication Date
JP2008512920A JP2008512920A (ja) 2008-04-24
JP2008512920A5 true JP2008512920A5 (enExample) 2008-10-16
JP4815572B2 JP4815572B2 (ja) 2011-11-16

Family

ID=35355255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007530809A Expired - Fee Related JP4815572B2 (ja) 2004-09-13 2005-08-30 補償された高速pll回路

Country Status (7)

Country Link
US (1) US8102215B2 (enExample)
EP (1) EP1792400B1 (enExample)
JP (1) JP4815572B2 (enExample)
CN (1) CN101019324B (enExample)
AT (1) ATE476015T1 (enExample)
DE (1) DE602005022599D1 (enExample)
WO (1) WO2006030335A2 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130702A (zh) * 2010-01-20 2011-07-20 北京迅光达通信技术有限公司 数字多信道无线收发信机

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63267822A (ja) 1987-04-23 1988-11-04 Hitachi Heating Appliance Co Ltd 開放型燃焼器の安全装置
JPH082020B2 (ja) * 1988-09-02 1996-01-10 日本電信電話株式会社 周波数シンセサイザ
JPH04196716A (ja) 1990-11-28 1992-07-16 Hitachi Ltd 位相同期回路
JPH04252621A (ja) * 1991-01-29 1992-09-08 Fujitsu Ltd 電圧制御発振器に加えるオフセット制御電圧の設定方法及び該方法による無線通信装置
JPH07202638A (ja) 1993-12-28 1995-08-04 Matsushita Electric Ind Co Ltd 電圧制御発振器
US6157271A (en) * 1998-11-23 2000-12-05 Motorola, Inc. Rapid tuning, low distortion digital direct modulation phase locked loop and method therefor
DE19926666A1 (de) * 1999-06-11 2000-12-14 Philips Corp Intellectual Pty Anordnung zur Offsetstromkompensation eines Phasendetektors
JP3488180B2 (ja) * 2000-05-30 2004-01-19 松下電器産業株式会社 周波数シンセサイザ
US6734749B2 (en) * 2001-05-29 2004-05-11 Telefonaktiebolaget Lm Ericsson (Publ) Direct modulated phase-locked loop
US6680654B2 (en) * 2001-10-24 2004-01-20 Northrop Grumman Corporation Phase locked loop with offset cancellation
JP2004080624A (ja) * 2002-08-21 2004-03-11 Matsushita Electric Ind Co Ltd 周波数シンセサイザ
US7548122B1 (en) * 2005-03-01 2009-06-16 Sequoia Communications PLL with switched parameters

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