Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
  • H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C3/00—Angle modulation
  • H03C3/02—Details
  • H03C3/09—Modifications of modulator for regulating the mean frequency
  • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
  • H03C3/0916—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop
  • H03C3/0925—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop applying frequency modulation at the divider in the feedback loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C3/00—Angle modulation
  • H03C3/02—Details
  • H03C3/09—Modifications of modulator for regulating the mean frequency
  • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
  • H03C3/0916—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop
  • H03C3/0933—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop using fractional frequency division in the feedback loop of the phase locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C3/00—Angle modulation
  • H03C3/02—Details
  • H03C3/09—Modifications of modulator for regulating the mean frequency
  • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
  • H03C3/0941—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation at more than one point in the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C3/00—Angle modulation
  • H03C3/02—Details
  • H03C3/09—Modifications of modulator for regulating the mean frequency
  • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
  • H03C3/0975—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation in the phase locked loop at components other than the divider, the voltage controlled oscillator or the reference clock
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

• the present invention relates to a phase-locked loop (PLL) circuit and a method of compensating such a PLL circuit to reduce settling times especially for first-order PLL loops.
• PLL phase-locked loop
• the term "first-order PLL” is used here to designate a PLL with no integration function (I-regulator term) in the Loop Filter.
• I-regulator term integration function
• PLL circuits comprise a phase/frequency detector, a loop filter, such as a low pass filter, a voltage-controlled oscillator (VCO), and if necessary, a frequency divider. If the clock frequency input to the phase detector and the output frequency of the VCO are equal, the frequency divider is not required.
• VCO voltage-controlled oscillator
• GSM Global System for Mobile communications
• a transmitting VCO In the Global System for Mobile communications (GSM) standard, a transmitting VCO must be able to lock a 100 MHz step to better than 90 Hz accuracy in less than 200 microseconds. This is due to the need to minimize current consumption (drain) by turning the transmit subsystem off when not in use and restart quickly upon turn on. It is furthermore important that this specification be met over a significant range of temperature and part variations.
• Conventional loop filter configurations can be inadequate due to the slowness of an Integral-regulator.
• the desired PLL bandwidth limits the possible speed of Integral-regulators due to the need of good stability margins at the loop.
• the bandwidth of a PLL is limited by requirements for filtering that is provided by a PLL.
• Conventional PLL circuits comprise charge-pump phase detectors, wherein the charge pump charges and discharges a capacitor in the low pass filter, depending upon advanced or delayed phase signals.
• the low pass filter then eliminates high frequency components and noise of the output voltage signal, which correspond to the phase difference.
• the low pass filter smoothes the phase difference signal to convert the same to a control voltage which is supplied to the VCO to control the oscillation frequency.
• the VCO is the most critical component of the PLL circuit.
• the output frequency dependence on the control voltage is determined by a conversion gain Vvco of the VCO. Due to the fact that the PLL circuit is a negative feedback loop, it functions to minimize the phase difference between the oscillation signal and a frequency input signal supplied to the phase detector.
• the phases of the two signals match with one another, i.e., the oscillation phase and frequency of the VCO output signal become the same as the phase and frequency of the frequency input signal.
• the input phase ⁇ j of the frequency input signal, the error phase ⁇ e at the output of the phase detector and the output phase ⁇ o at the VCO are zero at settled mode or state which may also be referred to as locked mode or state, or steady mode or state.
• a PLL circuit is named 'Second-Order-Loop', wherein this name is related to the number of integral terms 1/s in the Laplace transfer function of the open loop.
• the open-loop transfer function can be expressed as follows:
• F r (s) denotes the transfer function of a ripple filter which may be included in the loop filter
• Z LF denotes the impedance of the loop filter
• R denotes the resistance of a resistor and C the capacitance of a capacitor of an RC integration circuit of the loop filter
• K p denotes the transfer factor of the phase detector
• K 0 denotes the transfer factor of the VCO
• Document US 6,157,271 discloses a PLL circuit with rapid tuning function over a wide frequency range.
• a controller generates a digital open loop frequency control signal supplied to a digital-to-analog converter (DAC) which produces a variable DC reference potential.
• DAC digital-to-analog converter
• This reference potential is used as an open-loop tuning voltage added at the output of the phase detector to reduce acquisition time of the PLL circuit.
• an offset or compensation voltage is supplied to the loop filter means during a specific time phase of close-loop operation and the voltage value of the offset voltage is set in accordance with the characteristic of the voltage-controlled oscillator means. Due to the well- selected offset voltage, which has a function similar to the voltage at the integrating element of a second-order loop, it is possible to settle a first-order loop without huge steady-state phase errors. Applied to first-order loops, the suggested solutions leads to a loop settlement at much higher speed than second-order loops, which is highly valuable for a lot of applications. Furthermore, compensating means may be provided for generating a compensation current and for supplying the compensation current to an input of the loop filter means to compensate for a phase error of a phase detector means of the PLL circuit.
• the compensating means may comprise resistor means serially coupled between the voltage generator means and an input resistor of the loop filter means, wherein a current source may be connected in parallel to the resistor means.
• the setting means may be adapted to set the offset voltage to a value required at the input of the voltage-controlled oscillator to generate a desired output frequency.
• the offset voltage is set to about a value required according to the VCO curve for the desired frequency, so that the steady- state phase error can be significantly reduced.
• the setting means may be arranged to pre-select a characteristic curve of the voltage-controlled oscillator based on a desired output frequency of the voltage- controlled oscillator.
• the conversion characteristic of the voltage-controlled oscillator can be adapted to the desired frequency to thereby minimize steady-state phase errors.
• the setting means may be arranged to control the voltage- controlled oscillator so as to shift the VCO characteristic.
• the shifting of the VCO characteristic provides the advantage that a change of the tuning or control voltage of the voltage-controlled oscillator can be prevented.
• the shifting of the VCO characteristic is an alternative compared to DC settings at the Loop Filter in front of the VCO.
• Frequency- or Phase-Modulation for a transmitter can be injected at a PLL system in various manner but combined with above measures of compensating.
• Such a combination leads to an enhanced compensating means which may comprise first conversion means for converting an input modulation frequency into the compensation current.
• second conversion means may be provided for converting the modulation frequency into an input phase signal. This assures that the error phase is not changed when the modulation frequency is changed.
• third conversion means may be provided for converting the input modulation frequency into a divider factor of a fractional divider provided in the PLL circuit.
• the first and second conversion means can be used additionally and the modulation frequency can be directly supplied to the phase detector means.
• Fig. 1 shows a schematic block diagram of a PLL circuit according to the preferred embodiments
• Fig. 2 shows a schematic circuit diagram of an introduction of a compensation current to an offset voltage at a loop filter according to the preferred embodiments
• Fig. 3 shows a schematic frequency diagram indicating close-loop behavior of a PLL circuit
• Figs. 4a and 4b show schematic waveform diagrams indicating error phase behavior of different PLL loops
• Fig. 5 shows a schematic functional block diagram of a PLL circuit according to a first preferred embodiment
• Fig. 6 shows a schematic diagram indicating a shift of a VCO curve
• Fig. 7 shows a schematic functional block diagram of a PLL circuit according to a second preferred embodiment.
• Fig. 1 shows a schematic block diagram of a PLL circuit according to the preferred embodiments.
• the PLL circuit comprises a phase detector 10, a loop filter 20, which may be a low pass filter, a VCO 30, and a frequency divider 50.
• a compensation circuit 60 is provided which supplies a compensation current I 0 to a summing node 25 where the compensation current I 0 is added to a detection current I d which corresponds to the phase difference detected by the phase detector 10.
• a pre-selection circuit 40 is provided for pre-selecting a VCO curve or characteristic for a desired frequency fc H and the values of the divider ratio Nc H of the frequency divider 50, the conversion gain Kvco of the VCO 30 or at least one of these parameters. Furthermore, the pre-selection circuit 40 controls a voltage source 70 which is connected between the loop filter 20 and a reference potential, e.g. ground potential, to introduce an offset voltage Vi nt to the loop filter 20.
• a reference potential e.g. ground potential
• the phase detector 10 is a device, which detects the difference in phase between an input signal supplied to an input terminal 5 and an output signal of the VCO 30 supplied to an output terminal 15 and fed back via the frequency divider 50. Based on the difference between the two input signals, the phase detector 10 produces the detection current I d proportional to the amount of the phase difference.
• the input signal received at the input terminal 5 corresponds to a frequency reference signal and the output signal at the output terminal 15 corresponds to a feedback or output frequency signal.
• the loop filter 20 eliminates high frequency components and noise and smoothes the phase difference signal to convert the same to an error or control voltage which is supplied to the VCO 30 to control the oscillator frequency.
• the gain Kvco of the VCO 30 is associated with the voltage-to-frequency conversion.
• the frequency dependence on the control voltage is determined by this conversion gain Kvco of the VCO 30.
• the pre-selection circuit 40 is arranged to set the voltage Vj nt of the voltage source 70 to a value which the characteristic curve of the VCO 30 requires for generating a desired frequency. Or, alternatively, the pre-selection circuit 40 shifts the VCO curve.
• Fig. 2 shows a schematic circuit diagram as an option for adding the compensation current I c at the input of the loop filter 20.
• the circuitry of Fig. 2 can be used to replace the combination of the compensation block 60, the summing node 25 and the ((the)) loop filter block 20 in Fig. 1.
• the loop filter 20 which has an impedance Z LF comprises a ripple filter 22 with a transfer function F r which outputs the control or tune voltage Vtune to be supplied to the VCO 30.
• the loop filter 20 comprises a series connection of an input resistor of a resistance value (R - Rdi v ) and a divisional resistor Rdi v .
• the voltage source 70 is serially connected between the series connection of the input resistor and the divisional resistor, and a reference potential.
• the compensation current I c is a small current
• the parameter D indicates the damping or attenuation factor of the second-order term.
• the parameter (O n corresponds to the Eigen- frequency and the parameter (O A corresponds to the critical frequency which defines the corner for the slope with -20 dB/dec.
• Figs. 4a and 4b show schematic signaling or waveform diagrams indicating time behaviors of the error phase at the output of the phase detector 10 in case of a phase step of the input phase ⁇ j and the case of a frequency step at the input circular frequency (Bj, respectively.
• the phase response ⁇ eR (t) for a frequency step starts with a ramp and returns to zero with a speed depending on the damping factor D.
• the introduction of the pre-selection circuit 40 and the compensation circuit 60 serves to compensate the phase errors indicated in Figs. 4a and 4b.
• Fig. 5 shows a schematic functional block diagram of a PLL circuit according to the first preferred embodiment.
• the functional behavior of the phase detector is indicated by a subtraction node 12 and a conversion unit 14 with a conversion function or parameter Kp which expresses the conversion from the detected phase error ⁇ e to the detecting current I d .
• the compensation current I 0 is generated in the compensation unit 60 by a conversion unit 62 the function of which can be expressed by 1/RKvco which expresses the generation of the compensation current I c based on the input modulation frequency Oflb o cHn, where R corresponds to the resistance value of the input resistor of the loop filter 20 and Kvco corresponds to the conversion gain of the VCO 30.
• the input phase ⁇ is also generated from the input modulation frequency CObod j n using another conversion unit 90 which performs conversion based on the function 1/SN CH , where s denotes the Laplace operator.
• the sum of the compensation current I c and the detecting current Id is obtained at the summing node 25 and is supplied to the loop filter 20 to which the controllable voltage source 70 is connected, which generates the offset voltage Vj n t(fcH) as a function of the channel frequency fcH of the received transmission channel.
• the loop filter 20 converts the summed current into a tuning or control voltage V tune which is supplied to a subtracting node 32 of the VCO 30.
• a voltage V abs (fc H ) is subtracted to be able to increase the control voltage and thus present a realistic voltage range for the control voltage Vtune-
• the voltage difference Vo is supplied to a conversion unit 34 of the VCO 30, at which the voltage difference Vo is converted to an output signal N CH ⁇ O (S) which is the phase ⁇ ORF of the RF signal.
• the VCO output signal is supplied to the frequency divider 50 where it is divided by N CH to obtain the feedback phase ⁇ o which is compared at the phase detector with the input phase ⁇ j.
• a digital pre-selection of a VCO-curve for a desired channel frequency fcH and the values NCH, Kyco, V a bs and Vj nt (fcH) is performed in response to a start signal S.
• the offset voltage Vi nt and the characteristic of the VCO 30 are adjusted based on the desired frequency fcH to thereby increase the settling speed of the control loop in response to changes in the modulation frequency C ⁇ bode_m-
• the ripple filter function F r (s) can be an RC filter with no ohmic connection to ground.
• the input source of the loop filter 20 and the output load have high ohmic resistance values.
• the disadvantage of the remaining steady-state phase error shown in Fig. 4b can thus be minimized by introducing the offset voltage V m t and a DC compensation current I c .
• Fig. 5 shows a characteristic diagram of the conversion function of the VCO
• V a b S V a b S (fcH)-CQtaod_in/Kvco. Due to this shift, the frequency change ⁇ fOj is met at the initial control voltage V tune _o for the shifted curve. Thus, a change of the control voltage from Vtune o to Vtunej is not needed due to the change of the curve. Thereby, steady-state errors can be prevented.
• the shift of the VCO curve can be achieved by reducing the voltage at a varactor diode usually provided in VCOs like the VCO 30.
• Fig. 7 shows a schematic functional block diagram of an alternative second preferred embodiment, where the modulation frequency G ⁇ c ⁇ n is not fed to the phase input terminal of the phase detector via the conversion block 90 of Fig.5, but is supplied to a modified fractional divider 52.
• the new fractional divider 52 has a divider factor
• N Nc H +K mo d(t), wherein The factor Km O d(t) is a time-varying factor used for fractional-N transmission modulation.
• the modulation at the divider 52 serves to compensate modulation at ⁇ e .
• the modulation at the divider does the same as block 90 in Fig.5.
• a fractional-N synthesizer or frequency generator improves the integer-N design by replacing the conventional integer-N divider by the fractional-N divider 52 of Fig. 7.
• This fractional-N divider 52 effectively divides a frequency of the VCO 30 by a non- integer N, which may be a fraction, e.g., as high as N/(N+/-3).
• the frequency generator can step by e.g. N/(N+3) of a reference frequency ⁇ w.
• This improvement comes at the cost of introducing a spurious response generated by the fractional-N divider 52. Delay errors and periodic behavior in an accumulator of the fractional-N divider 52 cause these spurs.
• the loop filter 20 attenuates these spurs, which restricts the loop bandwidth to reduce the spurs to an acceptable level.
• the result compared to an integer-N divider in Fig. 5 is that the block 90 in Fig. 5 can be omitted but at the cost of introducing unwanted spurs.
• the modulation frequency C ⁇ mod in which may be a Gaussian Minimum Shift Keying (GMSK) modulation signal at baseband and which is digitally prepared, is supplied to a ratio determination unit 54, where the ratio between the modulation frequency cOmodjn and the reference frequency ⁇ w is calculated to obtain K mOd which is supplied to the fractional-N divider 52.
• the input modulation frequency 0Wd_m is supplied to the conversion unit 62 which may have a DAC function to generate the compensation current I c supplied to the summing node 25.
• a feedback frequency CCWk is obtained and supplied to a second subtraction node 56 (which may be included in block 10 of Fig. 1) where the reference frequency ⁇ w is subtracted and the difference is supplied to a conversion unit 92 (in mathematical terms because the phase is the integral over frequency, and 1/s represents integration) where the frequency difference is converted into a phase difference ⁇ o supplied to the first subtracting node 12.
• the control voltage Vtune is directly supplied to the conversion unit 34 which is now arranged to convert the control voltage Vmne into a frequency signal to which a radio channel frequency C0 RF _ CH is added at a second summing node 36 to obtain a radio frequency CO RF supplied to the fractional-N divider 52.
• the modulation output frequency of the PLL circuit is then obtained at the VCO 30 by generating the difference between the radio channel frequency C0 RF _ CH and the radio frequency CQRF at a third subtraction node 38.
• the PLL circuit or system according to the second preferred embodiment comprises a fractional-N synthesizer and a fractional-N transmission modulator. Modulation errors can be compensated by the compensation current I 0 .
• the integral regulator of a loop filter is replaced by introducing predetermined settings at the loop filter or at a voltage controlled oscillator.
• the compensation current I c may be implemented by the circuitry shown in Fig. 2.
• the movement of the VCO curve shown in Fig. 6 may be performed by the setting or pre ⁇ selection circuit 40, which is not explicitly shown in Fig. 7 but may as well be incorporated in the second preferred embodiment.
• fractional-N modulation can be used with pre-compensation and without two-point modulation.
• the DAC 62 of Fig. 7 is no longer required and an additional pre-compensation unit has to be added in front of the ratio determination unit 54.
• an additional pre-compensation unit requires exact knowledge of specific parameters of PLL circuit.
• this problem can be strongly alleviated if the I-regulator can be dispensed with, e.g. by using the pre-selection unit 40 of the above first and second embodiments.
• the combination of the pre-selection unit 40 with a fractional-N modulation with pre-compensation leads to an improved circuit behavior without requiring any two-point modulation.
• the settings of the pre-selection unit 40 for obtaining the values of Vint and/or the VCO characteristic can be stored or programmed during manufacturing of the PLL circuit.
• the function of the control functions are implemented as digital functions or software routines, which can be made variable until settling has finished, and are then fixed.
• the VCO characteristic curves can be switched in a stepwise manner during the settling process and can be fixed after the PLL circuit has settled.
• the offset voltage Vmt can be connected to any kind of loop filter at which a steady-state error signal is generated. Furthermore, any kind of current generation and current coupling technique can be used for adding the compensation current I c at the output of the phase detector 10 or the input of the loop filter 20.
• the preferred embodiments may thus vary within the scope of the attached claims.

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• 2005
  • 2005-08-30 JP JP2007530809A patent/JP4815572B2/ja not_active Expired - Fee Related
  • 2005-08-30 AT AT05781640T patent/ATE476015T1/de not_active IP Right Cessation
  • 2005-08-30 CN CN200580030555XA patent/CN101019324B/zh not_active Expired - Fee Related
  • 2005-08-30 US US11/575,214 patent/US8102215B2/en not_active Expired - Fee Related
  • 2005-08-30 EP EP05781640A patent/EP1792400B1/en not_active Ceased
  • 2005-08-30 WO PCT/IB2005/052840 patent/WO2006030335A2/en not_active Ceased
  • 2005-08-30 DE DE602005022599T patent/DE602005022599D1/de not_active Expired - Lifetime

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