JP2008501239A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2008501239A5 JP2008501239A5 JP2007515099A JP2007515099A JP2008501239A5 JP 2008501239 A5 JP2008501239 A5 JP 2008501239A5 JP 2007515099 A JP2007515099 A JP 2007515099A JP 2007515099 A JP2007515099 A JP 2007515099A JP 2008501239 A5 JP2008501239 A5 JP 2008501239A5
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- layer
- bonding
- channel region
- strain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 235000012431 wafers Nutrition 0.000 claims 13
- 239000010410 layer Substances 0.000 claims 10
- 239000000758 substrate Substances 0.000 claims 4
- 239000011229 interlayer Substances 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/856,581 US7041576B2 (en) | 2004-05-28 | 2004-05-28 | Separately strained N-channel and P-channel transistors |
| US10/856,581 | 2004-05-28 | ||
| PCT/US2005/014325 WO2005119746A1 (en) | 2004-05-28 | 2005-04-26 | Separately strained n-channel and p-channel transistors |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008501239A JP2008501239A (ja) | 2008-01-17 |
| JP2008501239A5 true JP2008501239A5 (enExample) | 2008-06-19 |
| JP4744514B2 JP4744514B2 (ja) | 2011-08-10 |
Family
ID=35459624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007515099A Expired - Fee Related JP4744514B2 (ja) | 2004-05-28 | 2005-04-26 | 集積回路の形成方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7041576B2 (enExample) |
| EP (1) | EP1749311A4 (enExample) |
| JP (1) | JP4744514B2 (enExample) |
| KR (1) | KR101149134B1 (enExample) |
| CN (1) | CN100508130C (enExample) |
| TW (1) | TWI416702B (enExample) |
| WO (1) | WO2005119746A1 (enExample) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7514767B2 (en) * | 2003-12-03 | 2009-04-07 | Advanced Chip Engineering Technology Inc. | Fan out type wafer level package structure and method of the same |
| US7459781B2 (en) * | 2003-12-03 | 2008-12-02 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
| US7348658B2 (en) * | 2004-08-30 | 2008-03-25 | International Business Machines Corporation | Multilayer silicon over insulator device |
| US8013342B2 (en) | 2007-11-14 | 2011-09-06 | International Business Machines Corporation | Double-sided integrated circuit chips |
| US7670927B2 (en) * | 2006-05-16 | 2010-03-02 | International Business Machines Corporation | Double-sided integrated circuit chips |
| KR100789570B1 (ko) * | 2006-08-23 | 2007-12-28 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
| US7485508B2 (en) * | 2007-01-26 | 2009-02-03 | International Business Machines Corporation | Two-sided semiconductor-on-insulator structures and methods of manufacturing the same |
| US7800150B2 (en) * | 2007-05-29 | 2010-09-21 | United Microelectronics Corp. | Semiconductor device |
| US8288756B2 (en) * | 2007-11-30 | 2012-10-16 | Advanced Micro Devices, Inc. | Hetero-structured, inverted-T field effect transistor |
| US20090289280A1 (en) * | 2008-05-22 | 2009-11-26 | Da Zhang | Method for Making Transistors and the Device Thereof |
| US8003454B2 (en) * | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
| US8193559B2 (en) * | 2009-01-27 | 2012-06-05 | Infineon Technologies Austria Ag | Monolithic semiconductor switches and method for manufacturing |
| TWI478319B (zh) * | 2010-07-20 | 2015-03-21 | 晶元光電股份有限公司 | 整合式發光裝置及其製造方法 |
| DE102010045055B4 (de) * | 2010-09-10 | 2019-03-28 | Austriamicrosystems Ag | Verfahren zur Herstellung eines Halbleiterbauelementes mit einer Durchkontaktierung |
| US8421193B2 (en) * | 2010-11-18 | 2013-04-16 | Nanya Technology Corporation | Integrated circuit device having through via and method for preparing the same |
| US9947688B2 (en) * | 2011-06-22 | 2018-04-17 | Psemi Corporation | Integrated circuits with components on both sides of a selected substrate and methods of fabrication |
| US8664756B2 (en) | 2012-07-24 | 2014-03-04 | Medtronic, Inc. | Reconstituted wafer package with high voltage discrete active dice and integrated field plate for high temperature leakage current stability |
| US8803292B2 (en) | 2012-04-27 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias and methods for forming the same |
| US8624324B1 (en) | 2012-08-10 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting through vias to devices |
| US10128269B2 (en) | 2013-11-08 | 2018-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Systems and methods for a semiconductor structure having multiple semiconductor-device layers |
| US10163897B2 (en) * | 2013-11-15 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inter-level connection for multi-layer structures |
| KR102530338B1 (ko) * | 2016-12-15 | 2023-05-08 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
| US11869890B2 (en) * | 2017-12-26 | 2024-01-09 | Intel Corporation | Stacked transistors with contact last |
| US11430814B2 (en) | 2018-03-05 | 2022-08-30 | Intel Corporation | Metallization structures for stacked device connectivity and their methods of fabrication |
| KR102746120B1 (ko) | 2019-03-11 | 2024-12-23 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| US11158738B2 (en) * | 2019-06-18 | 2021-10-26 | Samsung Electronics Co., Ltd | Method of forming isolation dielectrics for stacked field effect transistors (FETs) |
| WO2022201497A1 (ja) * | 2021-03-26 | 2022-09-29 | 昭和電工マテリアルズ株式会社 | 半導体装置の製造方法、半導体装置、集積回路要素、及び、集積回路要素の製造方法 |
| US12431469B2 (en) * | 2022-02-11 | 2025-09-30 | International Business Machines Corporation | Vertically stacked FET with strained channel |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6052052A (ja) * | 1983-08-31 | 1985-03-23 | Fujitsu Ltd | 相補型mis半導体装置 |
| JPS60154549A (ja) * | 1984-01-24 | 1985-08-14 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPS63126262A (ja) * | 1986-11-14 | 1988-05-30 | Sharp Corp | 三次元半導体集積回路の製造方法 |
| JPH02263465A (ja) * | 1988-11-05 | 1990-10-26 | Mitsubishi Electric Corp | 積層型半導体装置およびその製造方法 |
| JP3048686B2 (ja) * | 1991-07-22 | 2000-06-05 | 日本電気株式会社 | 半導体装置およびその製造方法 |
| JPH0714982A (ja) * | 1993-06-21 | 1995-01-17 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
| US5534713A (en) | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
| US5872393A (en) * | 1995-10-30 | 1999-02-16 | Matsushita Electric Industrial Co., Ltd. | RF semiconductor device and a method for manufacturing the same |
| US5936280A (en) * | 1997-04-21 | 1999-08-10 | Advanced Micro Devices, Inc. | Multilayer quadruple gate field effect transistor structure for use in integrated circuit devices |
| US5906951A (en) | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
| US5818069A (en) | 1997-06-20 | 1998-10-06 | Advanced Micro Devices, Inc. | Ultra high density series-connected transistors formed on separate elevational levels |
| JP4032454B2 (ja) * | 1997-06-27 | 2008-01-16 | ソニー株式会社 | 三次元回路素子の製造方法 |
| JP2000277715A (ja) * | 1999-03-25 | 2000-10-06 | Matsushita Electric Ind Co Ltd | 半導体基板,その製造方法及び半導体装置 |
| US6984571B1 (en) * | 1999-10-01 | 2006-01-10 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US6500694B1 (en) * | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US7008193B2 (en) * | 2002-05-13 | 2006-03-07 | The Regents Of The University Of Michigan | Micropump assembly for a microgas chromatograph and the like |
| TWI239051B (en) * | 2002-09-04 | 2005-09-01 | Penn State Res Found | Method for preparing a removable system on a mother substrate, method for preparing a sacrificial release layer on a mother substrate, and systems prepared thereby |
-
2004
- 2004-05-28 US US10/856,581 patent/US7041576B2/en not_active Expired - Fee Related
-
2005
- 2005-04-26 KR KR1020067027473A patent/KR101149134B1/ko not_active Expired - Fee Related
- 2005-04-26 CN CNB2005800152361A patent/CN100508130C/zh not_active Expired - Fee Related
- 2005-04-26 JP JP2007515099A patent/JP4744514B2/ja not_active Expired - Fee Related
- 2005-04-26 EP EP05738546A patent/EP1749311A4/en not_active Withdrawn
- 2005-04-26 WO PCT/US2005/014325 patent/WO2005119746A1/en not_active Ceased
- 2005-05-19 TW TW094116365A patent/TWI416702B/zh not_active IP Right Cessation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2008501239A5 (enExample) | ||
| JP2009283496A5 (enExample) | ||
| JP2009060096A5 (enExample) | ||
| SG139657A1 (en) | Structure and method to implement dual stressor layers with improved silicide control | |
| JP2005086157A5 (enExample) | ||
| TW200608588A (en) | Structures and methods for heat dissipation of semiconductor integrated circuits | |
| TW200715566A (en) | Display device and method of manufacturing the same | |
| WO2008087763A1 (ja) | 半導体装置およびその製造方法 | |
| JP2015114460A5 (enExample) | ||
| JP2009514247A5 (enExample) | ||
| JP2006173432A5 (enExample) | ||
| JP2014229814A5 (enExample) | ||
| JP2009246352A5 (ja) | 薄膜トランジスタの作製方法 | |
| JP2010262977A5 (enExample) | ||
| JP2011009452A5 (enExample) | ||
| JP2004047608A5 (enExample) | ||
| JP2005072566A5 (enExample) | ||
| JP2006054425A5 (enExample) | ||
| US10396186B2 (en) | Thin film transistor, method for fabricating the same, display panel and display device | |
| TW200745710A (en) | Organic transistor and method for manufacturing the same | |
| JP2007059881A5 (enExample) | ||
| JP2008182124A5 (enExample) | ||
| EP1873838A4 (en) | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | |
| JP2010532578A5 (enExample) | ||
| SG155895A1 (en) | Method to enhance device performance with selective stress relief |