JP2008277393A - 実装構造体及びその製造方法 - Google Patents
実装構造体及びその製造方法 Download PDFInfo
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- JP2008277393A JP2008277393A JP2007116715A JP2007116715A JP2008277393A JP 2008277393 A JP2008277393 A JP 2008277393A JP 2007116715 A JP2007116715 A JP 2007116715A JP 2007116715 A JP2007116715 A JP 2007116715A JP 2008277393 A JP2008277393 A JP 2008277393A
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- melting point
- point metal
- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
【解決手段】本発明は、配線基板2と、配線基板2の上面に実装される半導体素子3とを備えた実装構造体1であって、配線基板2の上面に形成される複数の凹部21と、複数の凹部21の内周面に膜形成される導電層24と、半導体素子3の下面に形成され、凹部21に下端部が位置する凸部30と、を備え、導電層24と凸部30との間に、導電層24及び凸部30を構成する材料よりも融点の低い材料から成る低融点金属層25が形成されており、低融点金属層25は、凸部30と接する領域又は前記導電層24と接する領域の少なくとも一方に、接合層26が形成されていることを特徴とする。
【選択図】図3
Description
2 配線基板
21 凹部
24 導電層
25 低融点金属層
26 接合層
3 半導体素子
30 バンプ(凸部)
Claims (7)
- 配線基板と、前記配線基板の上面に実装される半導体素子とを備えた実装構造体であって、
前記配線基板の上面に形成される複数の凹部と、
前記複数の凹部の内周面に膜形成される導電層と、
前記半導体素子の下面に形成され、前記凹部に下端部が位置する凸部と、を備え、
前記導電層と前記凸部との間に、前記導電層及び前記凸部を構成する材料よりも融点の低い材料から成る低融点金属層が形成されており、
前記低融点金属層は、前記凸部と接する領域又は前記導電層と接する領域の少なくとも一方に、接合層が形成されていることを特徴とする実装構造体。 - 請求項1に記載の実装構造体において、
前記接合層は、前記低融点金属層との界面が凹凸状に形成されていることを特徴とする実装構造体。 - 請求項2に記載の実装構造体において、
前記接合層は、前記低融点金属層との界面の最大高さ(Rz)が、3μmから10μmであることを特徴とする実装構造体。 - 請求項1乃至請求項3のいずれかに記載の実装構造体において、
前記接合層は、錫、インジウム又はビスマスから成る低融点金属材料と、銅、銀又は金から成る高融点金属材料と、を含有することを特徴とする実装構造体。 - 凹部の内周面に導電層を有する基板と、凸部を有する半導体素子とを準備する工程と、
前記凹部の導電層上に、前記導電層及び前記凸部を構成する材料よりも融点の低い材料から成る低融点金属層を膜形成する工程と、
前記凹部に前記凸部を進入し、前記凸部と前記低融点金属層とを接する工程と、
前記凸部及び前記低融点金属層を加熱し、前記凸部及び前記低融点金属層を発熱反応させ、前記凸部と前記低融点金属層との間に、前記凸部と前記低融点金属層との間の隙間を埋める接合層を形成する工程と、
を備えたことを特徴とする実装構造体の製造方法。 - 凹部の内周面に導電層を有する基板と、凸部を有する半導体素子とを準備する工程と、
前記凸部の表面に、前記導電層及び前記凸部を構成する材料の融点よりも低い融点の材料から成る低融点金属層を膜形成する工程と、
前記凹部に前記凸部を進入し、前記導電層と前記低融点金属層とを接する工程と、
前記導電層及び前記低融点金属層を加熱し、前記導電層及び前記低融点金属層を発熱反応させ、前記導電層と前記低融点金属層との間に、前記導電層と前記低融点金属層との間の隙間を埋める接合層を形成する工程と、
を備えたことを特徴とする実装構造体の製造方法。 - 請求項5又は請求項6に記載の実装構造体の製造方法において、
前記低融点金属層を加熱する温度は、前記低融点金属層を構成する材料の融点未満の温度であって、前記低融点金属層を構成する材料の融点より−100℃以上の温度であることを特徴とする実装構造体の製造方法。
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JP2007116715A JP4994099B2 (ja) | 2007-04-26 | 2007-04-26 | 実装構造体の製造方法 |
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JP2007116715A JP4994099B2 (ja) | 2007-04-26 | 2007-04-26 | 実装構造体の製造方法 |
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JP2008277393A true JP2008277393A (ja) | 2008-11-13 |
JP4994099B2 JP4994099B2 (ja) | 2012-08-08 |
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JP2007116715A Expired - Fee Related JP4994099B2 (ja) | 2007-04-26 | 2007-04-26 | 実装構造体の製造方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190044418A (ko) * | 2017-10-20 | 2019-04-30 | 삼성전기주식회사 | 다층 인쇄회로기판 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03218036A (ja) * | 1990-01-23 | 1991-09-25 | Sumitomo Electric Ind Ltd | 半導体素子実装用基板 |
JP2003230980A (ja) * | 2002-02-14 | 2003-08-19 | Nippon Steel Corp | 無鉛ハンダ合金、ハンダボール及びハンダバンプを有する電子部材 |
JP2004356195A (ja) * | 2003-05-27 | 2004-12-16 | Seiko Epson Corp | 電子部品の実装方法、電子部品の実装構造、電子部品モジュールおよび電子機器 |
JP2008153548A (ja) * | 2006-12-19 | 2008-07-03 | Fujitsu Ltd | 半導体装置 |
-
2007
- 2007-04-26 JP JP2007116715A patent/JP4994099B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03218036A (ja) * | 1990-01-23 | 1991-09-25 | Sumitomo Electric Ind Ltd | 半導体素子実装用基板 |
JP2003230980A (ja) * | 2002-02-14 | 2003-08-19 | Nippon Steel Corp | 無鉛ハンダ合金、ハンダボール及びハンダバンプを有する電子部材 |
JP2004356195A (ja) * | 2003-05-27 | 2004-12-16 | Seiko Epson Corp | 電子部品の実装方法、電子部品の実装構造、電子部品モジュールおよび電子機器 |
JP2008153548A (ja) * | 2006-12-19 | 2008-07-03 | Fujitsu Ltd | 半導体装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190044418A (ko) * | 2017-10-20 | 2019-04-30 | 삼성전기주식회사 | 다층 인쇄회로기판 |
KR102449368B1 (ko) * | 2017-10-20 | 2022-09-30 | 삼성전기주식회사 | 다층 인쇄회로기판 |
TWI788346B (zh) * | 2017-10-20 | 2023-01-01 | 南韓商三星電機股份有限公司 | 多層印刷電路板 |
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