JP2008244498A - ラップアラウンド・フランジ界面用の接触処理を用いる半導体製造 - Google Patents
ラップアラウンド・フランジ界面用の接触処理を用いる半導体製造 Download PDFInfo
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Abstract
【解決手段】半導体デバイスを製造する際に形成されるラップアラウンド接触領域用のフランジ界面は、耐久性および信頼性の高い電気的結合をもたらす。ウェハの第1の面上に、第1の材料を有する第1の層を形成する。トレンチ内で第1の層の一部が露出されるようにウェハの第2の面からトレンチを形成する。第2の層の一部が、トレンチ内で露出された第1の層の部分に接触するように、ウェハの第2の面上に、第2の材料を有する第2の層を形成する。トレンチを介してウェハを分離する。トレンチは、ウェハの第2の面の、トレンチを形成すべき領域を切削することによって形成することができる。次いで、トレンチが形成されるようにウェハをエッチングすることができる。
【選択図】 図32
Description
本出願は、1994年5月4日に米国特許商標庁に出願された開示文書第353620号に関連する。
(関連出願)
本出願は、下記の米国特許出願に関連する。
(1)「Fabricating a Semiconductor with an Insulative Coating」と題する、1992年5月27日に出願された米国特許出願第07/889832号
(2)1992年5月27日に出願された米国特許出願第07/889832号の分割出願であり、「Fabricating a Semiconductor with an Insulative Coating」と題する、1993年4月9日に出願された米国特許出願第08/045584号
本発明の一目的は、耐久性および信頼性がかなり高い電気装置を提供することである。
本発明の他の目的は、電気ボンディングを向上させる耐久性および信頼性の高い接触界面を含む電気装置を提供することである。
本発明の他の目的は、電気ボンディングを向上させるために導電側壁とフランジ界面とを有する接触領域を含む電気装置を提供することである。
本発明の他の目的は、導電ブリッジ構造と、導電側壁を有し、電気ボンディングを向上させる導電ブリッジ構造とのフランジ界面を形成する、接触領域とを含む電気装置を提供することである。
ウェハの第2の面上に、第2の材料を有する第2の層を形成する。第1の層と第2の層は、半導体ウェハのエッジにフランジ界面を形成する。
(詳細な説明)
下記の詳細な説明では、ラップアラウンド・フランジ界面用の接触処理を用いる半導体製造に関する本発明による特定の実施形態について述べる。下記の説明では、本発明を完全に理解していただくために、特定の寸法、材料、処理シーケンス、半導体デバイスなど多数の特定の詳細について述べる。しかし、当業者には、これらの特定の詳細なしで本発明を実施できることが自明であろう。他の例では、本発明を不必要にあいまいにしないように、周知の処理ステップ、機器などについて特に詳しくは説明しない。
図2は、ダイオード・モジュール200、すなわち本発明の一実施形態の斜視図を示す。ダイオード・モジュール200は、様々な素子またはデバイスのうちの1つを含むことができる。ダイオード・モジュール200はたとえば、PINダイオードまたはNIPダイオードを含むことができる。ダイオード・モジュール200は、スイッチとして使用すべき直列素子を含むことができる。ダイオード・モジュール200は、ショットキー気密ダイオードを含むことができる。ダイオード・モジュール200は、直列分路素子を含むことができる。ダイオード・モジュール200を装置または前述の素子やデバイスなど様々な素子またはデバイスのうちの1つを含む電気装置とも呼ぶ。ダイオード・モジュール200をデバイスとも呼ぶ。
上層250は、適当な絶縁材料を含むことができる。たとえば、上層250は、エポキシ、または二酸化ケイ素(SiO2)、または窒化ケイ素(Si3N4)、またはプラスチック、またはテフロン(登録商標)、またはポリイミド、またはガラスを含むことができる。上層250は、他の誘電材料または絶縁材料、あるいは材料の組合せを含むことができる。上層250は、ダイオード・モジュール200を保護するように働く。上層250は、受動層として働く。上層250は、ダイオード・モジュール200を機械的に保持するように働くこともできる。
または銅(Cu)を使用することができる。酸化インジウムチタン(ITO)または酸化金すず(ATO)を使用することもできる。他の金属、または金属を含む材料の組合せを使用することもできる。
この絶縁層は、他の材料、または材料の組合せを含むこともできる。この絶縁層は次いで、たとえばフォトリソグラフィ技法およびエッチング技法を使用して領域411ないし413としてパターン化することができる。
図34は、トランジスタ・モジュール500、すなわち本発明の一実施形態の斜視図を示す。トランジスタ・モジュール500を装置または電子装置と呼ぶ。トランジスタ・モジュール500をデバイスとも呼ぶ。
すなわち、Ti−Wは、相互接続層の底部と接触層594ないし595の頂部に付着させる。その結果、この実施形態では、各相互接続層と各接触層594ないし595とのそれぞれの間に耐久性および信頼性の高い金属間表面間結合部が形成される。他の実施形態では、相互接続層と接触層584ないし585とのそれぞれの間に結合部を作製する際にTi−Wではなく他の材料を使用することができる。この場合、同じ材料を使用することによって、相互接続部と接触層594ないし595とのそれぞれの間での耐久性および信頼性の高い結合部の形成を容易にすることができる。他の実施形態では、相互接続部と接触層594ないし595をそれぞれ結合するために使用される材料はそれぞれ、異なるものでよい。
図87は、集積回路900を、それを製造するための半導体ウェハ901に関連して示すものである。集積回路900は本発明の一実施形態である。集積回路900はたとえば、1つまたは複数のトランジスタと、ダイオードと、抵抗器と、その他の回路要素とを含むことができる。集積回路900は、たとえば半導体(CMOS)回路や、バイポーラ回路や、ひ化ガリウムで構成することができる。集積回路900を装置、または様々な素子またはデバイスのうちの1つを含む電気装置とも呼ぶ。集積回路900をデバイスとも呼ぶ。
202:活性接合領域
221:第1の相互接続層
222:第2の相互接続層
250:上層
266:トレンチまたはギャップ
271:第1の絶縁層
272:第2の絶縁層
280:第1の接触層
281:第2の接触層
286:デバイス半導体領域
287:半導体ポスト領域
Claims (3)
- (a) 上面を有するデバイス半導体領域(1002)と、
(b) エッジを有する上面と側壁とを有する半導体ポスト領域(1085)と、
(c) デバイス半導体領域(1002)の上面上の領域に結合され、半導体ポスト領域(1085)の上面上に形成され、半導体ポスト領域(1085)のエッジ上に延び、且つ第1の導電材料(1022)を含む第1の層(1022)と、
(d) 半導体ポスト領域(1085)の側壁上に形成され、第2の導電材料(1091)を含み、第1(1022)及び第2(1091)の層のフランジ界面が半導体ポスト領域(1085)のエッジのところで形成されるように、半導体ポスト領域(1085)のエッジのところで第1の層(1022)に接着された第2の層(1091)とを備える電気装置。 - 第1の層(1022)が、第1の導電材料を含む第1の複数の材料を含み、第2の層(1091)が、第2の導電材料を含む第2の複数の材料を含み、第1の導電材料がチタンタングステンを含み、第2の導電材料がチタンタングステンを含み、第1の複数の材料が金を含み、第2の複数の材料がニッケルを含むことを特徴とする請求項1に記載の電気装置。
- 電気装置が構成要素の1つとして集積回路を含み、デバイス半導体領域(1002)が集積回路の一部として回路を含み、第1の層(1022)がこの回路に電気的に結合されていることを特徴とする請求項1に記載の電気装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/241,602 | 1994-05-11 | ||
US08/241,602 US5656547A (en) | 1994-05-11 | 1994-05-11 | Method for making a leadless surface mounted device with wrap-around flange interface contacts |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP52966995A Division JP4159599B2 (ja) | 1994-05-11 | 1995-04-27 | ラップアラウンド・フランジ界面用の接触処理を用いる半導体製造 |
Publications (2)
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JP2008244498A true JP2008244498A (ja) | 2008-10-09 |
JP4804510B2 JP4804510B2 (ja) | 2011-11-02 |
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JP52966995A Expired - Fee Related JP4159599B2 (ja) | 1994-05-11 | 1995-04-27 | ラップアラウンド・フランジ界面用の接触処理を用いる半導体製造 |
JP2008151663A Expired - Fee Related JP4804510B2 (ja) | 1994-05-11 | 2008-06-10 | 導電側壁とフランジ界面とを有する接触領域を含む電気装置 |
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JP52966995A Expired - Fee Related JP4159599B2 (ja) | 1994-05-11 | 1995-04-27 | ラップアラウンド・フランジ界面用の接触処理を用いる半導体製造 |
Country Status (8)
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US (2) | US5656547A (ja) |
JP (2) | JP4159599B2 (ja) |
KR (1) | KR100343030B1 (ja) |
AU (1) | AU2366795A (ja) |
DE (1) | DE19580514B4 (ja) |
GB (1) | GB2302210B (ja) |
HK (1) | HK1012776A1 (ja) |
WO (1) | WO1995031829A1 (ja) |
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Also Published As
Publication number | Publication date |
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GB2302210B (en) | 1998-09-16 |
DE19580514T1 (de) | 1997-06-19 |
KR970703046A (ko) | 1997-06-10 |
JP4804510B2 (ja) | 2011-11-02 |
GB9623266D0 (en) | 1997-01-08 |
JPH10504135A (ja) | 1998-04-14 |
WO1995031829A1 (en) | 1995-11-23 |
GB2302210A (en) | 1997-01-08 |
DE19580514B4 (de) | 2010-10-07 |
JP4159599B2 (ja) | 2008-10-01 |
AU2366795A (en) | 1995-12-05 |
HK1012776A1 (en) | 1999-08-06 |
US5656547A (en) | 1997-08-12 |
KR100343030B1 (ko) | 2002-12-05 |
US5557149A (en) | 1996-09-17 |
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