WO1990015438A1

WO1990015438A1 - Beam lead and semiconductor device structure and method for fabricating integrated structure

Info

Publication number: WO1990015438A1
Application number: PCT/US1989/002514
Authority: WO
Inventors: Michael W. Busby; Richard J. Pommer; Tony K. Johnson; Jeffrey J. Waxweiler; Martin Camen
Original assignee: Unistructure, Inc.
Priority date: 1989-06-08
Filing date: 1989-06-08
Publication date: 1990-12-13

Abstract

Beams leads (10) are epitaxially grown on a semiconductor chip (12) separated from a wafer, forming an integral structure. The beam leads (10) are embedded within a dielectric material (20) for protection and strength. The dielectric material (20) covers the active circuit side (14) as well as edges (16) of the semiconductor chip (12), and extend beyond the area of the semiconductor chip while enclosing the leads, to provide means within the integral structure for supporting the semiconductor chip. The semiconductor chip (12) has its active circuit side hermetically sealed. A method for fabricating the integral semiconductor chip and beam lead structure is also disclosed.

Description

-I- TϊRRM τ.V.Afo RTfT> SEMICONDUCTOR DEVICE

STRUCTURE AND METHOD FOR FABRICATING

INTEGRATED STRUCTURE

Background of the Invention Field of the Invention;

The present invention relates to the art of semiconductor and like circuit component interconnects, and more particularly to semiconductor devices having leads formed from the device for support and interconnection to circuit elements.

Description of the Prior Art;

In the past, semiconductor devices, such as integrated circuit chips, have been fabricated in large numbers on a single silicon wafer. Advancing technology has enabled the fabrication of chips with smaller features, but the chips must be interconnected in order to be used. The interconnection is made usually by leads connected at one of their ends to contact points or terminal pads initially formed on the chips, and at their other ends to the next level of interconnection circuitry.

The leads frequently are formed on lead frames which comprise a plurality of sets of finger-like leads formed from a metallic layer on an inεulative layer. The insulative layer has apertures centrally located in the frame, into which the inner ends of the leads extend in cantilever fashion for interconnection, usually be metallurgically bonding to the connector or contact points or pads of the chip, which is designed to be placed within the central aperture. The aperture is designed so that the leads, when in their originally formed positions, will precisely position over connection or contact points or terminal pads on the semiconductor chip. Sets of outer ends of the leads have pads formed thereon for interconnection with the next levels of the interconnection circuitry. A more detailed description of such a structure may be seen in, for example, United States Patent No. 3,689,991 issued to Aird.

The finger-like leads are very fine, fragile and delicate, and are formed spaced very close to each other. In handling prior to connection with a semiconductor chip, the fragile finger leads frequently are bent or are moved or displaced merely with casual contact. Often, the finger leads are bent or displaced in the vertical direction, so that no connection can be made with the semiconductor device. If an effort is made to re-bend or straighten the end of the lead, it will likely break off because it is so fragile. Additionally, when incorrect connections are made, the fault is not discovered until the chip is assembled and fails in routine testing. The chip must then be discarded. Moreover, the leads, which typically have a thickness of approximately 0.002 inch, are frequently damaged by abrasive contact during handling, resulting in an incomplete lead width, which changes the pre-designed resistance, or in an open circuit. Consequently, there has been little or no testing of lead frames before chip assembly because contact will bend or destroy the leads before connection to the chip.

Methods and apparatus have been suggested in the past to alleviate this problem. For example, it has been suggested to provide a semiconductor wafer over which lies an insulating layer and a plurality of multi-layer beam lead assemblies, each of which comprises a contact portion overlaying the insulating layer. The beam lead assembly comprises an aperture to contact the wafer and a cantilevered terminal portion integral with the wafer contact portion to provide mechanical support for the wafer, as described in United States Patent No. 3,426,252 issued to Lepselter.

Such solutions help to alleviate the problem. The solution suggested requires the building up of the multi- layers of the lead assemblies on the silicon wafer, with the leads extending cantilevered beyond the individual chips on the wafer. It is desired, however, to provide integral i semiconductor chip and lead structures without sacrificing area on a silicon wafer.

It is desired further to provide an integrated semiconductor chip and lead structure having leads embedded within a supporting dielectric that protects the leads. It is desired yet further to provide a semiconductor chip and lead structure having a greater density of leads, or capable of providing more leads for the chip or device. It is also desired to provide an integrated semiconductor chip and lead structure where the chip is hermetically sealed in the fabricating process.

Methods of fabricating integrated chip and lead structures are sought where a plurality of the integrated structures are fabricated together on a single panel, and on which the entire plurality of structures can be tested simultaneously and with the support of the panel structure or of the substrate on which the integrated chip and lead structures are grown or built up.

Summary of the Invention In brief, in accordance with one aspect of the present invention, an integral semiconductor chip and beam lead structure has a chip with a dielectric material formed in a layer over the chip's active circuit side and over adjacent edges. Connecting posts and beam leads are epitaxially grown from the chip, with the dielectric material surrounding the posts and beam leads. Additional posts, also surrounded by the dielectric material, are formed having ends exposed and plated for protection, to provide contact points or pads for next level interconnect circuitry. The active circuit side of the chip can be hermetically sealed prior to forming the dielectric layer.

The integral chip and lead structure is formed by initially separating a plurality of semiconductor devices such as chips from the wafer upon which they were fabricated. Each chip is positioned on a brass substrate and within an aperture in a second layer substrate also comprised of brass with the active circuit side of the chip facing upward and substantially in the common plane of the outside surface of the second brass substrate layer. Initially, posts or vias are built up from the active circuit side of the chip from the contact points or pads of the chip. A hermetic sealant, such as silicon nitride, can be deposited upon the active circuit side of the chip to hermetically protect the chip. A dielectric layer is formed over the chip and around portions of the chip's edges adjacent the active circuit side surface of the chip, leaving the ends of the posts exposed for interconnection with leads to be formed. The beam leads are then formed on the dielectric material in a predetermined design having the leads connected at one end to the posts or vias. Additional posts or vias are built up at predetermined points and ends of the leads. The leads are covered and the posts are surrounded by a further deposition of the dielectric material to completely embed the leads within. The posts have a portion left exposed, which is plated with a protective layer of gold or suitable conductive and protective layer.

Additional parallel planes or layers of the beam leads can be formed upon the dielectric layer embedding the beam leads built up in the initial layer. The dielectric layer embedding the leads provides the structural strength necessary for supporting the chip and lead structure when it is placed in use in, for example, a circuit board or other application.

A third set of contact points is formed in the structure for connection with an edge card connector connecting a test board which tests the chip and lead connections and operation. The substrate is removed from the chip and beam lead portion of the structure, but not from the remaining portion to provide strength to the structure during the testing procedures. After testing, the portion of the structure containing the third set of contact points is separated to result in the integral chip and beam lead structure. Other novel features which are believed to be characteristic of the invention, both as to organization and methods of operation, together with further objects and advantages thereof, will be better understood from the following description in which preferred embodiments of the invention are described by way of example.

Brief Description of the Drawings Fig. 1 is a partial perspective view of the preferred embodiment of the present invention showing a chip having beam leads built up therefrom;

Fig. 2 is a partially cut-away, side elevational cross- section view of the chip and beam lead structure of the preferred embodiment of Fig. 1;

Figs. 3A through 3K are cross-sectional, partial elevation views showing the method of fabricating the chip and beam lead structure of the preferred embodiment of the present invention; and

Fig. 4 is a partially cut-away, side elevational cross- section view showing an alternative embodiment of the invention of Fig. 1.

Description of the Preferred Embodiments A semiconductor device and beam lead structure 10, reference being had initially to Figs. 1 and 2 of the accompanying drawings, comprises a semiconductor chip 12 having its active circuit side 14 and at least portions of adjacent edges 16 covered with a dielectric layer 20. The dielectric layer 20 embeds beam leads 22 for interconnecting the chip 12 with next level interconnect circuitry, not shown. The beam leads 22 have inner ends 24. Each inner end 24 has a post or via 26 which is formed in conductive contact with contact points or terminal pads 28 of the chip 12, through to the surface of the dielectric layer 20 substantially coplanar with the chip's active circuit side 14.

Each of the beam leads 22 further has an outer end 30 comprising an upper surface contact pad 32 and lower surface contact pad 34. The contact pads 32, 34 are exposed through their corresponding upper and lower surfaces of the dielectric layer 20 which extends beyond the planar limits of the chip's active circuit side 14. The contact pads 32, 34 are positioned for conductive contact with the next level interconnect circuitry. As shown in Fig. 2, beam leads 22 with embedding dielectric layers 20 can be formed in an alternative embodiment in layers above or parallel to other layers- of the beam leads 22. The dielectric layer 20 completely embeds the leads 22 and surrounds the posts 24 and a portion of the contact pads 32, 34. The dielectric layer 20 has sufficient strength to support the chip 12 when the outer ends of the leads 22 are interconnected to next level circuitry. The dielectric layer 20 is sufficiently bonded or formed onto the chip 12 so that it will carry the chip 12. The dielectric layer 20 is integrated with the chip not only at the active circuit side 14, but also at least portions of the adjacent edges 16 to both protect the chip, as will be explained in greater detail below, and to create a greater integration or bond with the chip 12. Thus, the chip 12 and dielectric layer 20, having the beam leads 22 embedded within it, comprise an integrated structure 10 wherein the chip 12 has integral attaching and structural supporting means in the form of the integrated dielectric layer 20. The thickness of the dielectric layer 20 for one layer of beam leads 22 is on the order of approximately 0.005 inch, which is to be compared to typical thicknesses of semiconductor chips of approximately 0.015 inch to 0.030 inch. It has been found that the leads 22 can be formed much closer together and still be reliably useful for interconnection with semiconductor devices when the leads 22 are embedded within the dielectric layer 20. A close pitch for the inner end 24 spacing for the leads 22 can be especially useful if it is desired to manufacture a chip having closer pitch between its terminal pads, in order either to manufacture a chip having more terminal pads or connector points, or to manufacture a smaller chip having the same number of interconnecting terminal pads. The leads are not susceptible to bending and cross-over with adjacent leads, and the spacing between adjacent leads becomes merely a matter of design choice and chip terminal pad limitations. It is believed that useful beam leads having a pitch of as low as 2 mils or even 0.5 mil at the inner ends is possible with this structure.

The chip and beam lead embedded in a dielectric layer structure 10 is made in this embodiment by a method in which the chip 12 is first removed or severed from the silicon wafer on which the chip 12 was originally formed.

Initially, as shown in Fig. 3A, a brass substrate 40 is formed. A second layer 42 of a brass substrate is formed on top of the first layer 40, but having apertures 44 for receiving the severed chip 12 so that the active circuit side 14 of the chip 12 positions substantially in the plane of the surface of the second substrate layer 42. Other suitable, removable substrates may be employed, such as, for example, aluminum, copper or readily soluble organic material.

As indicated, the top or exposed surface of the second brass layer 42 should be in substantially the same plane as the active circuit side 14 of the chip 12, as shown in Fig. 3B, or preferably within 0.001 inch of it. The level could be accomplished by machining the aperture 44 depth to match the height of the chip 12. Alternatively, the first layer 40 could be built up on the back of the second layer 42 after the chip 12 is positioned within its respective aperture 44 and the corresponding surfaces of the chip 12 and substrate 42 are positioned coplanarly. Those skilled in the art may perceive other methods.

Photoresist and additive metalization techniques are then used to establish a pattern of lower contact pads 48 on the top of the second brass layer 42. Initially, an adhesion and barrier layer, such as nickel-vanadium, and then a layer of copper are laid over the chip surface 14 and the co-planar surface of second brass layer 42 for later electroplating steps. A layer of photoresist is then laid on the copper layer, is exposed and developed in the desired pattern of the outer contact pads 48. A protective metal 50 such as gold is deposited in the remaining holes of the photoresist pattern. A suitable barrier such as nickel is then deposited on the gold pattern 50. The lower outer contact pad 48 then has post 52 built up on the gold protective layer 50. The photoresist material is then removed.

Using similar photoresist and additive metalization techniques, copper posts or vias 26 are built up from the contact points or terminal pads 28 of the chip 12. The terminal pad 28 on a chip 12 has a slight recess from the surface 14 of the chip 12. The build up of the copper post 26 into and up from this contact point or terminal pad 26 provides for a more secure interlock between the chip 12 and the post 26. The photoresist material and the initial copper layer and barrier layer under the photoresist are then removed.

If desired, a protective coating 46 of silicon nitride or other hermetic sealant is deposited over the surface 14 of the chip 12 and down the surface of the side edges 16. The silicon nitride sputter is made after the photoresist material and initial copper layer are removed and before the deposition of the initial amount of the dielectric material 60, to be explained in greater detail below. The silicon nitride coating 46 will be removed from the points over the connector points or terminal pads 28 of the chip when the dielectric layer 60 is abraded, as explained below.

A layer of dielectric material 60 is then laid, as seen in Fig. 3C. The dielectric material may be a polyimide, silicone, epoxy or combination of these or other suitable dieleσtric material. Preferably, the dielectric will result in the least expansive stresses between the chip 12, the dielectric layer 60, the posts 26, 52, 78 and the leads 22 while providing sufficient strength in the extensions from the chip 12 to support the chip 12 and protect the leads 22. The relative thicknesses of the dielectric layer 20 with the chip 12 is on the order of from 1:3 to 1:6, thus reducing the effect of a differential in the coefficients of expansion between the two elements. A dielectric which cures without stressful procedures is also preferred. Thus, a cure which does not require excessive heating or like stresses is preferred.

The dielectric material covering the tops of the posts 26, 52, as seen in Fig. 3D, is removed by abrading, leaving a pattern of lower inner and lower outer pads or contact connections. Also, when the dielectric material 60 is removed or abrade from the surface of the posts, the silicon nitride coating 46 covering the tops of the thus constructed posts 26 is also abraded away, exposing the tops of the posts 26 for conductive connection with the leads to be formed, thus eliminating the need for a special etching step to remove the silicon nitride.

A layer of photoresist 62 is then laid on the top surface. A pattern of leads for connecting the inner ends 24 and the outer ends 30 and corresponding contact pads is established by exposing and developing the photoresist, leaving depressions where the desired leads 22 should be. Copper is then electroplated into three depressions to form the leads 22. A layer of copper is then sputtered over the result to form a common for later electroplating steps.

In an alternative embodiment, the silicon nitride coating 46 may be deposited on the active circuit side 14 of the chip 12, and down adjacent edges 16 initially, before the build up of the posts 26 and 52. The silicon nitride coating 46 will then be etched away from the area over the contact points of the chip 12 before the deposition of the copper layer and photoresist in the procedures set forth herein above. Additional photoresist 64 is laid on the structure. Again, the photoresist is exposed and developed for the areas above the lower outer contact posts 52. Copper is electroplated into the depressions formed by the removed photoresist to form the posts 66 opposite the leads from the lower outer posts 52, to result in posts to support upper outer contact pads 32, as shown in Fig. 3F. The photoresist is then removed, as seen in Fig. 3G.

Additional dielectric material 60 is laid over the leads 22 and upper posts 66, as shown in Fig. 3H, so that the additional dielectric material coalesces with the initial deposition of dielectric material to form a substantially integral mass of dielectric embedding the leads and surrounding the posts 26, 52, 66. Again, the dielectric material above the posts 66 is abraded or otherwise removed to expose the upper surface of the copper post 66, as shown in Fig. 31. Additional copper is built up by electroplating over the exposed posts 66 to form a bump 68 raised above the post 66. The bump 68 is electroplated with a protective layer 70 of nickel and gold, as shown in Fig. 3J. The brass substrates 40 and 42 are then stripped away, Fig. 3K, to result in the chip and beam lead structure 10. The lower outer post 52 has its contact pad 50 exposed for connection. The dielectric layer 60 firmly embeds and supports the leads 22 and provides a structural support for the chip 12 when the outer contact pads 50, 70 are bonded to the next level interconnection circuitry. The dielectric layer 60 also grips the chip along the edges 16 adjacent the active circuit surface 14 of the chip 12, to afford a greater support for the chip when the structure 10 is connected in the next level interconnection circuitry.

Additionally, after the substrates are removed from beneath the lower outer contact pads 50, bumps could be built up thereover, if desired. The bump would be of copper and electroplated by additive metalization techniques as described hereinabove. A protective coating or layer similar to the gold and nickel plating 70 of the pad for the upper outer contact pad could then be formed. Such a bump built up may be beneficial for chip face-up mounting.

It may be appreciated that neither the thicknesses nor -li¬ the distances shown in the accompanying drawings are to scale. The chip 12 is relatively much more thick than the dielectric layer 60. The chip 12 has a thickness typically on the order of approximately from 0.015 inch to 0.030 inch, while the dielectric layer 60 has a thickness of approximately 0.005 inch in the preferred embodiment. The expansion characteristic of the chip and beam lead structure 10 is governed principally by the coefficient of expansion of the chip 12, thus relieving much of the stress found in lead frames and other structures used to interconnect semiconductor chips and devices.

In another alternative embodiment, the first brass layer 40 and portions of the second brass layer 42 that underly the outer lead ends 30, 50 can then be removed, leaving the remaining portions 71 of the first brass layer and 72 of the second brass layer to provide mechanical backing and support for the chip and beam lead structure 10, as seen in Fig. 4, for purposes as will be explained in greater detail below. Simultaneously with the build up of the leads 22 and connected inner contact posts 26 and outer contact pads 32, 34, a third set of upper contact pads 76 are built, as shown in Fig. 4. The third set of contact pads 76 are used in testing the chip and beam lead structure 10. The remaining portions 71, 72 of the substrates 40, 42 provide satisfactory support for inserting the contact pads 76 into an edge card connector 78 for connection to a test board. Leads 80 in the connector 78 conductively contact the contact pads 76 through spring biased contacts 82 for connection to a test circuit. The circuit connection of the chip and beam lead structure 10 can then be tested without destructive contact with the leads or their outer contact pads 32, 34. Upon successful test results, the chip and beam lead structure 10 is excised from the third set of contact pads 76 and from the supporting first and second substrate portions 71, 72 to result in the chip and beam lead structure 10 as shown in Fig. 3K. Alternative testing constructions may be used. For example, lead wires from a test circuit could be soldered or otherwise attached to the contact points 76. In such an arrangement, the lead wires would be removed or separated after testing, when the third set of contact points or pads are excised from the chip and beam lead structures.

The foregoing detailed description of my invention and of preferred embodiments, as to products, compositions and processes, is illustrative of specific embodiments only. It is to be understood, however, that additional embodiments may be perceived by those skilled in the art. The embodiments described herein, together with those additional embodiments, are considered to be within the scope of the present invention.

Claims

E CLAIM:

1. A semiconductor device structure comprising beam leads epitaxially grown from contact pads of a semiconductor device and wherein said leads are embedded in a dielectric material.

2. The semiconductor device structure of Claim 1 wherein said semiconductor device comprises at least one planar surface having edges extending therefrom, and wherein said dielectric material covers at least a portion of said edges and said at least one surface.

3. The semiconductor device structure of Claim 2 wherein said dielectric material embedding beam leads extends beyond the edges of said device.

4. The semiconductor device structure of Claim 1 wherein all of said beam leads are positioned in at least one layer.

5. The semiconductor device structure of Claim 4 wherein said leads are positioned in a plurality of layers, and wherein each of said leads is embedded in a dielectric material.

6. The semiconductor device structure of Claim 1 having a lead pitch of less than six thousandths of an inch.

7. The semiconductor device structure of Claim 1 comprising leads in a density of greater than one hundred and sixty-six leads per inch epitaxially grown therefrom.

8. The semiconductor device structure of Claim 1 wherein said semiconductor device has an active circuit side which is hermetically sealed.

9. The semiconductor device structure of Claim 8 wherein at least one surface of said semiconductor device is coated with silicon nitride.

10. The semiconductor device structure of Claim 1 wherein said beam leads embedded in said dielectric material extend beyond the semiconductor device, and further comprising: a first set of contact pads formed extending from a corresponding beam lead at a position beyond said semiconductor device; a second set of contact pads extending from a corresponding beam lead at a position more distant beyond said semiconductor device than said first set of contact pads; and support means for supporting said second set of contact pads when said second set of contact pads are inserted in testing means for testing semiconductor device and beam lead interconnections.

11. A method of fabricating an integral semiconductor device and beam lead structure comprising the steps of: placing a semiconductor device on a removable substrate wherein said semiconductor device and said substrate have at least one substantially common plane; forming on said semiconductor device conductive posts raised from said plane; forming on said semiconductor device and said substrate a dielectric layer comprised of dielectric material surround said posts; abrading said dielectric layer to expose each of said posts; forming conductive leads covering said posts and in a predetermined design on said dielectric layer to form leads; and forming a dielectric layer on and surrounding said leads to completely embed said leads within said dielectric material, leaving said beam lead exposed at one end for interconnection with additional circuitry.

12. The method of Claim 11 further comprising the step of forming a conductive and protective material on said leads to form at least one contact pad for each of said leads.

13. The method of Claim 11 further comprising, after the step of forming conductive leads, the steps of: forming conductive posts extending from said leads on said dielectric layer; in said step of forming said dielectric layer on and surround said leads, the further step of surrounding with said dielectric layer said posts extending from said leads; abrading said dielectric material to expose each of said posts; and forming a conductive and protective material on said posts to form at least one contact pad for each of said leads.

14. The method of Claim 11 wherein said step of forming on said semiconductor device and said substrate a dielectric layer, said dielectric layer is formed around edges of said semiconductor device.

15. The method of Claim 11 further comprising the step of hermetically sealing said semiconductor device with a hermetic sealant which is formed on exposed surfaces and edges of said semiconductor device and around said posts extending from said common plane.

16. The method of Claim 15 wherein said step of hermetically sealing said device is conducted after forming conductive posts raised from the plane on said semiconductor device.

17. The method of Claim 15 wherein said step of hermetically sealing said device is conducted before forming conductive posts raised from the plane on said semiconductor device, and further comprising the step of removing said sealant from contact points on said semiconductor device.

18. The method of Claim 15 wherein said hermetic sealant comprises silicon nitride.

19. The method of Claim 13 further comprising the steps of: forming a first set of contact pads on said conductive posts to result in a first set of contact pads positioned a distance beyond said semiconductor device; forming a second set of contact pads extending from a corresponding beam lead at a position more distant beyond said semiconductor device than said first set of contact pads; and support means for supporting said second set of contact pads when said second set of contact pads are inserted in testing means for testing semiconductor device and beam lead interconnections.

20. The semiconductor device and beam lead structure made by the process of Claim 11.

21. A method of fabricating an integral semiconductor device and beam lead structure by separating a semiconductor device from its water and building up from said device, using photoresist and metalization techniques, beam leads.

22. The structure made by the process of Claim 21.

23. The structure of Claim 22 wherein said beam leads are embedded within a dielectric material which extends beyond said semiconductor device and is capable of structurally supporting said semiconductor device.