KR100336769B1 - Chip size package and the manufacturing method - Google Patents

Abstract

The present invention relates to a wafer-level chip size package and a method of manufacturing the same. The present invention relates to a wafer chip having a chip pad formed at a predetermined position, an insulating dielectric layer formed on an upper side of the wafer chip to expose an upper surface of the chip pad, A low modulus polymer layer (hereinafter referred to as an LMP layer) formed locally on an upper surface of the insulating dielectric layer, a metal wiring layer formed on an upper side of the insulating dielectric layer so as to electrically connect the LMP layer and the chip pad, and an upper side of the LMP layer. A wafer-level chip size package including a solder mask polymer layer formed on the upper surface of the metal wiring layer so that the upper surface of the metal wiring layer positioned on the upper surface of the metal wiring layer, and solder balls bonded to the upper surface of the metal wiring layer on the upper side of the LMP layer, and fabricated therein By providing a method, thermal stress caused by the difference in coefficient of thermal expansion between the wafer chip and the circuit board To a locally formed in only where needed, without forming a front surface of the wafer chip, as the existing LMP layer formed on the lower side solder balls to absorb it to the improved reliability and fairness of the solder joint at the same time.

Description

Wafer-level chip size package and its manufacturing method {CHIP SIZE PACKAGE AND THE MANUFACTURING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer-level chip size package and a method of manufacturing the same, and more particularly, to a low modulus polymer layer formed below a solder ball to absorb thermal stress caused by a difference in thermal expansion coefficient between a wafer chip and a circuit board. The LMP layer) is not formed on the entire surface of the wafer chip as in the prior art, but relates to a wafer-level chip size package having a structure formed locally only on a necessary portion and a manufacturing method for manufacturing the same.

The most important thing in the chip size package of the wafer level is to ensure the solder joint reliability.

In order to secure the reliability of such solder joints, the compliant layer is applied in the conventional package. First, as shown in FIG. 1, the LMP layer (5) is adhered or coated with a solid or liquid low modulus polymer on the front of the package. ) Is formed on the entire surface of the package, and second, the conductive polymer layer 17 is formed between the solder ball 20 and the metal wiring 15 after the package process is completed, as shown in FIG. 2.

In the above, reference numerals 1 and 11 which are not described refer to chips, and reference numerals 3 and 13 denote chip pads formed on the chips 1 and 11. In addition, reference numerals 9 and 19 denote polymer layers for solder masks formed to make a place for the solder balls 10 and 20, and reference numerals 7 and 15 denote solder balls 10 and 20 and chip pads 3 and 13. It shows a metal wiring layer formed to be electrically connected. Finally, reference numeral 14 denotes an insulating dielectric layer formed between the chip 11 and the metallization layer 15.

However, in the case of forming the LMP layer 5 by attaching the solid low modulus polymer to the front surface of the package, the above-described conventional techniques can be implemented at the package level as shown in FIG. Difficulties have made it impossible to implement at the wafer level.

In addition, in the case of forming a LMP layer by coating a liquid low modulus polymer on the entire surface of the packager, a wafer level can be implemented, but physical properties between the wafer chip and the LMP layer, that is, a coefficient of thermal expansion and strength, etc. There was a problem that the difference between the large and difficult to secure the adhesive force.

In addition, when the conductive polymer layer 17 is formed between the solder ball 20 and the metallization layer 15 after finishing the packaging process, the conductive polymer layer 17 is expensive and economical. In addition to the fall, the components of the foreign material are composed of a metal and a polymer, so the electrical conductivity is poor, there is a problem that is not suitable for high-speed memory.

The object of the present invention devised in view of the above-described problems is that the LMP layer formed on the lower side of the solder ball to absorb the thermal stress caused by the difference in the coefficient of thermal expansion between the wafer chip and the circuit board, as the conventional The present invention provides a wafer-level chip size package and a method of manufacturing the same, which are formed locally on only necessary portions to improve processability and reliability of solder bonding at the same time.

In addition, an additional object of the present invention is to increase the adhesion between the LMP layer and the metal wiring layer by changing the shape of the LMP layer formed locally on the lower side of the solder ball, and to increase the contact area between the metal wiring layer and the solder ball, the metal wiring layer and the solder ball. The present invention provides a wafer-level chip size package and a method of manufacturing the same, which can disperse thermal stress generated therebetween so that the reliability of the solder joint can be further improved.

1 is a block diagram showing a cross-sectional structure of a micro-VISA according to the prior art

2 is a block diagram showing a cross-sectional structure in the case of using a conductive polymer layer as a compliant layer of the chip size package according to the prior art,

3 is a configuration diagram showing a cross-sectional structure of a chip size package at the wafer level according to the first embodiment of the present invention;

4a to 4l is a configuration diagram showing a manufacturing method for manufacturing the first embodiment of the present invention described above,

5 is a configuration diagram showing a cross-sectional structure of a wafer-level chip size package according to a second embodiment of the present invention;

6A to 6H are diagrams illustrating a manufacturing method for manufacturing the above-described second embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

50, 150: wafer chip 51, 151: chip pad

53, 153: dielectric dielectric layer 55, 155: low modulus polymer layer

57, 157: metal wiring layer 59, 159: polymer layer for solder mask

61, 161: solder ball 154: high modulus polymer layer

In order to achieve the object of the present invention as described above, a wafer chip having a chip pad formed at a predetermined position, an insulating dielectric layer formed on the upper side of the wafer chip so that the top surface of the chip pad is exposed, and locally on an upper surface of the insulating dielectric layer. An LMP layer formed on the upper surface of the metal interconnection layer and an upper surface of the metal interconnection layer disposed on the upper side of the insulating lead layer to electrically connect the LMP layer and the chip pad; A wafer level chip size package is provided comprising a solder mask polymer layer and solder balls bonded to an upper surface of the metal interconnect layer on the upper side of the LMP layer.

In addition, according to the present invention, a wafer chip having a chip pad formed at a predetermined position, an insulating dielectric layer formed on an upper side of the wafer chip so that the top surface of the chip pad is exposed, and a high modulus polymer layer partially formed on an upper surface of the insulating dielectric layer (Hereinafter referred to as an HMP layer), an LMP layer formed on an upper surface of a portion of the insulating dielectric layer in which the HMP layer is not formed, and a metal wiring layer formed on the HMP layer to electrically connect the LMP layer and the chip pad. And a solder mask polymer layer formed on the upper surface of the metal wiring layer so that the upper surface of the metal wiring layer positioned on the upper side of the LMP layer is exposed, and solder balls bonded to the upper surface of the metal wiring layer on the upper side of the LMP layer. A level chip size package is provided.

In addition, according to the present invention, the first step of forming an insulating dielectric layer on the upper side of the wafer chip so that the upper surface of the chip pad formed on the wafer chip, and locally forming the LMP layer only in the position where the solder ball of the insulating dielectric layer is seated A second process of forming a metal wiring layer on an upper side of the insulating dielectric layer so that the solder balls and the chip pads can be electrically connected to each other, and an upper surface of the metal wiring layer located on the upper side of the LMP layer. And a fourth process of forming a solder mask polymer layer on the upper side of the wiring layer and a fifth process of bonding the solder ball by performing a reflow process after seating the solder ball on the metal wiring layer on the upper side of the LMP layer. A method of manufacturing a chip size package of a wafer level is provided.

In addition, according to the present invention, after forming an insulating dielectric layer on the upper side of the wafer chip so that the upper surface of the chip pad formed on the wafer chip is exposed, an HMP layer is formed on the upper surface of the remaining portion except the position where the solder ball is to be seated And a second process of forming an LMP layer on an upper surface of the portion of the dielectric dielectric layer in which the HMP layer is not formed, and a metal wiring layer on the upper side of the HMP layer to electrically connect the solder ball and the chip pad. And a fourth process of forming a polymer layer for solder mask on the upper side of the metal interconnection layer so that the upper surface of the metal interconnection layer positioned on the upper side of the LMP layer is exposed, and a solder ball on the metal interconnection layer on the upper side of the LMP layer. After the step of performing a reflow process to bond the solder ball to the wafer level between the chips, characterized in that The method of manufacturing a package is provided.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a diagram illustrating a cross-sectional structure of a wafer-level chip size package according to a first embodiment of the present invention, and FIGS. 4A to 4L illustrate a manufacturing method for manufacturing the first embodiment of the present invention. The configuration diagram shown.

As shown in FIG. 3, the chip size package of the wafer level according to the first embodiment of the present invention is a wafer chip 50 having a chip pad 51 formed at a predetermined position, and an upper surface of the chip pad 51. An insulating dielectric layer 53 formed on the wafer chip 50 so as to be exposed, an LMP layer 55 locally formed on an upper surface of the insulating dielectric layer 53, the LMP layer 55, and a chip pad 51. The metal wiring layer 57 formed on the upper side of the dielectric dielectric layer 53 and the upper surface of the metal wiring layer 57 located on the upper side of the LMP layer 55 so as to be electrically connected to each other. A solder mask polymer layer 59 formed on the upper side and a solder ball 61 bonded to the upper surface of the metal wiring layer 57 on the upper side of the LMP layer 55 are included.

Here, the LMP layer 55 is formed to be inclined in the outward direction from the upper side to the lower side so that the adhesive force with the metal wiring layer 57 is improved.

A manufacturing method for manufacturing a chip size package having the above structure will be described below with reference to FIGS. 4A to 4L.

First, in order to form the insulating dielectric layer 53 on the upper side of the wafer chip 50 so that the upper surface of the chip pad 51 formed on the wafer chip 50 is exposed, the entire dielectric dielectric layer on the upper surface of the wafer chip 50 ( After coating 53), the portion of the insulating dielectric layer 53 positioned above the chip pad 51 is removed to open the chip pad 51 (FIG. 4A) (FIG. 4B).

Thereafter, the LMP layer 55 is locally formed only at the position where the solder ball 61 is seated in the insulating dielectric layer 53 (FIGS. 4E and 4F).

The process of forming the LMP layer 55 will be described in more detail. A low modulus polymer such as silicon base or polymide is spin coated on the entire surface of the wafer chip 50. After coating, soft baking is performed to form the LMP layer 55 (FIG. 4C).

Then, after the photoresist (PR) is applied to the entire surface of the LMP layer 55, the photoresist is selectively exposed, developed, and etched so that the photoresist remains only at the position where the solder ball 61 is seated (FIG. 4D). .

Thereafter, the LMP layer 55 is etched so that the outer surface of the LMP layer 55 protected by the photoresist is formed to be inclined in an outward direction from the upper side to the lower side according to baking conditions during soft baking. When the photoresist is peeled off, the LMP layer 55 in which the outer surface is inclined is formed locally only at the position where the solder ball 61 on the wafer chip 50 is seated (FIG. 4E) (FIG. 4F).

At this time, the inclining of the outer surface of the LMP layer 55 is to increase the adhesion to the metal wiring layer 57 to be formed later, the inclination angle of the outer surface of the LMP layer 55 and the horizontal plane is It is preferable to set it as 70 degrees or less.

When the LMP layer 55 is formed as described above, the metal wiring layer 57 is formed on the insulating dielectric layer 53 so that the solder balls 61 and the chip pads 51 can be electrically connected to each other (FIG. 4G) ( Figure 4h) (Figure 4i).

That is, a metal material such as titanium or aluminum / nickel / copper is deposited by sputtering on the entire surface of the wafer chip 50, and then a metal wiring layer 57 having a predetermined pattern is formed using a lithography process.

Subsequently, a solder mask polymer layer 59 is formed on the entire surface of the wafer chip 50 to form a place where the solder ball 61 is placed on the wafer chip 50, and then the solder mask polymer is formed by using a lithography process. The upper portion of the LMP layer 55, which is the portion where the solder ball 61 is to be placed, is removed from the layer 59 (FIG. 4J) (FIG. 4K).

When the solder ball 61 is placed as described above, the solder ball 61 is seated on the metal interconnection layer 57 on the upper side of the LMP layer 55, and then the solder ball 61 is bonded by performing a reflow process ( 4L).

Meanwhile, FIG. 5 is a diagram illustrating a cross-sectional structure of a wafer-level chip size package according to a second embodiment of the present invention, and FIGS. 6A to 6H are manufactured to manufacture the second embodiment of the present invention. The method is a schematic diagram.

In the chip size package of the wafer level according to the second embodiment of the present invention, as shown in FIG. 5, a wafer chip 150 having a chip pad 151 formed at a predetermined position and an upper surface of the chip pad 151 are formed. An insulating dielectric layer 153 formed on the wafer chip 150 to be exposed, a high modulus polymer layer (hereinafter referred to as an HMP layer) 154 partially formed on an upper surface of the insulating dielectric layer 153, and the insulating oil The HMP layer 154 to electrically connect the LMP layer 155 and the LMP layer 155 and the chip pad 151 formed on an upper surface of the entire layer 153 in which the HMP layer 154 is not formed. A solder mask polymer layer 159 formed on the metal wiring layer 157 so that the metal wiring layer 157 formed on the upper side of the metal wiring layer 157 and the upper surface of the metal wiring layer 157 located on the upper side of the LMP layer 155 are exposed. And a solder ball 161 bonded to an upper surface of the metal wiring layer 157 on the upper side of the LMP layer 155.

Here, the LMP layer 155 has a contact area between the solder ball 161 and the metal wiring layer 157 so that the thermal stress is not concentrated at the corners of the contact portions of the solder ball 161 and the metal wiring layer 157. The central portion is formed in a concave shape.

A manufacturing method for manufacturing a chip size package having the above structure will be described below with reference to FIGS. 6A to 6H.

First, in order to form an insulating dielectric layer 153 on the upper side of the wafer chip 150 so that the top surface of the chip pad 151 formed on the wafer chip 150 is exposed, the entire dielectric dielectric layer ( After coating 153, the portion of the insulating dielectric layer 153 located above the chip pad 151 is removed to open the chip pad 151 (FIG. 6A).

Subsequently, a high modulus polymer is coated on the entire surface of the wafer chip 150 to form the HMP layer 154 only in the remaining portion of the insulating dielectric layer 153 except for the position where the solder ball 161 is seated. After removing the portion positioned on the chip pad 151 and the portion where the solder ball 161 is to be placed, the chapter pad 151 and the solder ball 161 are opened to open (FIG. 6B).

Thereafter, the LMP layer 155 is formed only on the upper surface of the portion of the insulating dielectric layer 153 where the HMP layer 154 is not formed, that is, the position where the solder ball 161 is to be seated.

If the LMP layer 155 is formed in more detail, the low modulus polymer is coated on the entire surface of the wafer chip 150 by spin coating to have a uniform thickness, and then soft-baked to form the LMP layer. The photoresist is formed on the entire surface of the LMP layer 155 and the photoresist is selectively exposed, developed, and etched to form the solder ball 161. To remain (FIG. 6C).

In this case, the portion of the LMP layer 155 formed in the place where the solder ball 161 is to be placed is concave concave when compared with other portions because the HMP layer 154 of the portion is formed in an open form.

Subsequently, the remaining portion of the LMP layer 155 except for the portion protected by the photoresist is etched to form an LMP layer 155 having a concave shape in the center thereof and peeling off the remaining photoresist (FIG. 6D) ( 6e).

In this case, forming the LMP layer 155 in a concave shape of the center portion may widen the contact area between the metal wiring layer 157 and the solder ball 161 to be formed on the LMP layer 155 in the same shape. This is to prevent the thermal stress from being concentrated at the corners of the contact portions between the solder balls 161 and the metal wiring layer 157.

When the LMP layer 155 is formed as described above, the metal wiring layer 157 is formed on the upper side of the HMP layer 154 so that the solder balls 161 and the chip pads 151 may be electrically connected to each other (FIG. 6F).

That is, a metal material such as titanium or aluminum / nickel / copper is deposited on the entire surface of the wafer chip 150 by sputtering, and then a metal wiring layer 157 having a predetermined pattern is formed by using a lithography process.

In this case, the portion of the metal wiring layer 157 positioned on the LMP layer 155 is formed in the same shape as that of the upper surface of the LMP layer 155, that is, concavely recessed.

Subsequently, a solder mask polymer layer 159 is formed on the entire surface of the wafer chip 150 to form a place where the solder ball 161 is placed on the wafer chip 150, and then the solder mask polymer is formed using a lithography process. The upper portion of the LMP layer 155, which is the portion where the solder ball 161 is placed, is removed from the layer 159 (FIG. 6G).

When the solder ball 161 is placed as described above, the solder ball 161 is seated on the metal wiring layer 157 on the upper side of the LMP layer 155, and then the solder ball 161 is bonded by performing a reflow process ( 6h).

As described above, the wafer-level chip size package and the manufacturing method thereof according to the present invention, the solder ball 61 to absorb the thermal stress caused by the difference in thermal expansion coefficient between the wafer chip (50, 150) and the circuit board. , LMP layers 55 and 155 formed under the 161 are not formed on the entire surface of the wafer chips 50 and 150 as in the prior art, but are locally formed only in necessary portions, thereby improving processability and reliability of solder bonding at the same time. .

That is, according to the present invention, the LMP layers 55 and 155 are locally formed to minimize the deterioration of adhesion due to the difference in physical properties between the wafer chips 50 and 150 and the LMP layers 55 and 155, thereby improving the reliability of the package. There is this.

In addition, the present invention may increase the adhesive strength between the LMP layer 55 and the metal wiring layer 57 by changing the shape of the LMP layers 55 and 155 formed locally on the lower side of the solder balls 61 and 161, or the metal wiring layer. The contact area between the 157 and the solder ball 161 may be widened to disperse thermal stress generated between the metal wiring layer 157 and the solder ball 161, thereby improving solder joint reliability.

Claims (8)

delete delete A wafer chip having a chip pad formed at a predetermined position, an insulating dielectric layer formed on an upper side of the wafer chip so that the top surface of the chip pad is exposed, and a high modulus polymer layer partially formed on an upper surface of the insulating dielectric layer (hereinafter referred to as an HMP layer). ), An LMP layer formed on an upper surface of the portion of the dielectric dielectric layer in which the HMP layer is not formed, a metal wiring layer formed on an upper side of the HMP layer to electrically connect the LMP layer and a chip pad, and an upper side of the LMP layer. And a solder mask polymer layer formed on the upper surface of the metal wiring layer so that the upper surface of the metal wiring layer positioned on the upper surface of the metal wiring layer is exposed, and solder balls bonded to the upper surface of the metal wiring layer on the upper side of the LMP layer. The method of claim 3, wherein The LMP layer has a contact area between the solder ball and the metal wiring layer, so that a center portion of the LCP layer is formed in a concave shape so that thermal stress is not concentrated at a corner portion of the contact portion between the solder ball and the metal wiring layer. package. Forming an insulating dielectric layer on the upper side of the wafer chip to expose the upper surface of the chip pad formed on the wafer chip; A first step of forming a LMP layer by applying a low modulus polymer to the entire surface of the wafer chip by spin coating, followed by soft baking, and selectively exposing the photoresist to the front surface of the LMP layer, exposing and developing the photoresist. After etching, the second step of leaving the photoresist only in the place where the solder ball is to be seated, and after etching the LMP layer so that the outer surface of the LMP layer protected by the photoresist is formed to be inclined outward from the upper side to the lower direction A second step of removing the photoresist, wherein the LMP layer is locally formed only at the position where the solder ball is to be seated in the dielectric dielectric layer; A third process of forming a metal wiring layer on the upper side of the insulating dielectric layer to electrically connect the solder balls and the chip pads, and a solder mask on the upper side of the metal wiring layer so that the top surface of the metal wiring layer located on the upper side of the LMP layer is exposed. And a fifth process of forming a polymer layer for the polymer layer and a fifth process of bonding the solder balls by reflowing the solder balls after depositing the solder balls on the metal wiring layer on the upper side of the LMP layer. Manufacturing method. delete Forming an insulating dielectric layer on the upper side of the wafer chip to expose the upper surface of the chip pad formed on the wafer chip, and then forming an HMP layer on the upper surface of the remaining portion except for the position where the solder ball is to be seated; A second process of forming an LMP layer on an upper surface of a portion of the dielectric dielectric layer in which the HMP layer is not formed, and a third process of forming a metal wiring layer on the upper side of the HMP layer so that the solder balls and the chip pad may be electrically connected to each other; And a fourth process of forming a solder mask polymer layer on the upper side of the metal wiring layer so that the upper surface of the metal wiring layer positioned on the upper side of the LMP layer is exposed, and depositing solder balls on the metal wiring layer on the upper side of the LMP layer. And a fifth process of bonding the solder balls to each other. The method of claim 7, wherein The second process is a first step of applying a low modulus polymer to the entire surface of the wafer chip to a uniform thickness by spin coating and then soft baking to form an LMP layer, and after applying a photoresist to the entire surface of the LMP layer Selectively exposing, developing, and etching the photoresist, leaving the photoresist only at the position where the solder ball is to be seated, and etching the remaining portion of the LMP layer except for the portion protected by the photoresist, and the center is concave. And a third step of peeling off the remaining photoresist after forming the LMP layer.