KR20010061792A - Wafer level package - Google Patents
Wafer level package Download PDFInfo
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- KR20010061792A KR20010061792A KR1019990064334A KR19990064334A KR20010061792A KR 20010061792 A KR20010061792 A KR 20010061792A KR 1019990064334 A KR1019990064334 A KR 1019990064334A KR 19990064334 A KR19990064334 A KR 19990064334A KR 20010061792 A KR20010061792 A KR 20010061792A
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- metal
- pattern film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
Abstract
Description
본 발명은 웨이퍼 레벨 패키지에 관한 것으로서, 보다 구체적으로는 웨이퍼상태에서 패키징 공정이 이루어지는 패키지에 관한 것이다.The present invention relates to a wafer level package, and more particularly, to a package in which a packaging process is performed in a wafer state.
기존의 패키지는 웨이퍼를 먼저 스크라이브 라인을 따라 절단하여 개개의 반도체 칩으로 분리한 후, 개개의 반도체 칩별로 여러 가지 패키징 공정을 실시하는 것에 의해 제조되었다.Existing packages are manufactured by first cutting a wafer along a scribe line, separating the wafer into individual semiconductor chips, and then performing various packaging processes for each semiconductor chip.
그러나, 상기된 기존의 패키지는 개개의 반도체 칩별로 많은 단위 공정이 실시되어야 하기 때문에, 하나의 웨이퍼에서 제조되는 반도체 칩들을 고려하게 되면, 공정수가 너무 많다는 문제점을 안고 있다.However, since the conventional package described above requires many unit processes to be performed for each semiconductor chip, considering the semiconductor chips manufactured from one wafer, there is a problem that the number of processes is too large.
그래서, 최근에는 웨이퍼를 먼저 절단하지 않고 웨이퍼 상태에서 상기된 패키징 공정을 우선적으로 실시한 후, 최종적으로 스크라이브 라인을 따라 절단하여 패키지를 제조하는 방안이 제시되었다. 이러한 방법으로 제조된 패키지를 웨이퍼 레벨 패키지라 하는데, 이러한 종래의 패키지 3가지 유형을 도 1 내지 도 3을 참고로 하여 개략적으로 설명하면 다음과 같다.Therefore, in recent years, a method of manufacturing a package by first performing the above-described packaging process in a wafer state without cutting the wafer first and finally cutting along the scribe line has been proposed. A package manufactured in this manner is called a wafer level package. The three types of such conventional packages will be briefly described with reference to FIGS. 1 to 3.
먼저, 도 1을 참조로, 웨이퍼(1a)에 구성된 반도체 칩의 본드 패드(2a)가 웨이퍼(1a) 표면에 형성되어 있다. 본드 패드(2a)가 노출되도록, 폴리이미드와 같은 하부 절연층(3a)이 웨이퍼(1a) 표면에 형성되어 있다. 하부 절연층(3a) 표면에 하부 금속 패턴(4a)이 증착되어서 그의 일단이 본드 패드(2a)에 연결되어 있다. 하부 금속 패턴(4a)의 타단이 노출되도록, 폴리이미드와 같은 상부 절연층(5a)이 하부 절연층(3a) 표면에 형성되어 있다. 상부 절연층(5a)으로부터 노출된 하부 금속 패턴(4a)에 상부 금속 패턴(7a)이 증착되어 있다. 상부 금속 패턴(7a)에 솔더 볼(6a)이 마운트되어 있다.First, with reference to FIG. 1, the bond pad 2a of the semiconductor chip comprised in the wafer 1a is formed in the surface of the wafer 1a. The lower insulating layer 3a such as polyimide is formed on the surface of the wafer 1a so that the bond pads 2a are exposed. The lower metal pattern 4a is deposited on the surface of the lower insulating layer 3a, and one end thereof is connected to the bond pad 2a. An upper insulating layer 5a such as polyimide is formed on the surface of the lower insulating layer 3a so that the other end of the lower metal pattern 4a is exposed. The upper metal pattern 7a is deposited on the lower metal pattern 4a exposed from the upper insulating layer 5a. The solder ball 6a is mounted on the upper metal pattern 7a.
도 2에 도시된 패키지에서는 도전성 범프(3b)가 이용된다. 즉, 웨이퍼(1b) 표면에는 금속 패턴(4b)이 증착되어 그의 일단이 본드 패드(2b)에 전기적으로 연결되어 있다. 금속 패턴(4b)의 타단을 노출시키는 비아홀을 갖는 레진과 같은 절연층(5b)이 웨이퍼(1b) 표면에 형성되어 있다. 절연층(5b)에 형성된 비아홀에 도전성 범프(3b)가 형성되고, 금속막(7b)이 도전성 범프(3b) 표면에 도금된다. 솔더 볼(6b)이 금속막(7b)상에 마운트된다.In the package shown in Fig. 2, a conductive bump 3b is used. That is, the metal pattern 4b is deposited on the surface of the wafer 1b, and one end thereof is electrically connected to the bond pad 2b. An insulating layer 5b such as a resin having a via hole exposing the other end of the metal pattern 4b is formed on the surface of the wafer 1b. The conductive bumps 3b are formed in the via holes formed in the insulating layer 5b, and the metal film 7b is plated on the surface of the conductive bumps 3b. The solder ball 6b is mounted on the metal film 7b.
한편, 도 3에 도시된 패키지는 도 1 및 도 2에 도시된 패키지 구조와 유사하고, 다만 절연층으로 BCB라는 레진이 이용된다. 즉, 웨이퍼(1c) 표면에 본드 패드(1c)가 노출되도록, 하부 절연층(3c)이 형성되어 있다. 금속 패턴(4c)이 하부 절연층(3c) 표면에 증착되어 그의 일단이 본드 패드(2c)에 연결되어 있다. 금속 패턴(4c)의 타단이 노출되도록, 상부 절연층(5c)이 하부 절연층(3c) 표면에 형성되어 있다. 노출된 금속 패턴(4c)의 타단에 접합 보조층(7c)이 형성되고, 솔더 볼(6c)이 접합 보조층(7c)상에 마운트되어 있다.Meanwhile, the package shown in FIG. 3 is similar to the package structure shown in FIGS. 1 and 2, except that BCB is used as the insulating layer. That is, the lower insulating layer 3c is formed so that the bond pad 1c may be exposed on the surface of the wafer 1c. A metal pattern 4c is deposited on the surface of the lower insulating layer 3c so that one end thereof is connected to the bond pad 2c. The upper insulating layer 5c is formed on the surface of the lower insulating layer 3c so that the other end of the metal pattern 4c is exposed. The bonding auxiliary layer 7c is formed at the other end of the exposed metal pattern 4c, and the solder balls 6c are mounted on the bonding auxiliary layer 7c.
상기된 3가지 유형의 종래 웨이퍼 레벨 패키지에서는 본드 패드와 솔더 볼간의 접속 매개체로서, 모두 동일하게 금속 패턴이 적용된다. 그런데, 금속 패턴은 전술된 바와 같이, 이종 계열의 재질인 절연층 표면을 따라 배열되므로, 지지 구조가 매우 취약하다. 특히, 금속 패턴의 일부분이 솔더 볼이 마운트되는 볼 랜드로 이용되는데, 전술된 바와 같이 금속 패턴의 지지 구조가 매우 취약하기 때문에, 솔더 볼의 접합 강도도 당연히 취약해진다.In the above three types of conventional wafer level packages, the same metal pattern is applied as the connection medium between the bond pads and the solder balls. However, as described above, since the metal pattern is arranged along the surface of the insulating layer that is a heterogeneous material, the supporting structure is very weak. In particular, a part of the metal pattern is used as the ball land on which the solder ball is mounted. As described above, since the supporting structure of the metal pattern is very weak, the joint strength of the solder ball also becomes weak.
또한, 주지된 사실대로 반도체 칩과 패키지가 실장되는 보드간의 열팽창계수 차이는 매우 크다. 따라서, 반도체 칩과 보드의 신축 정도가 크게 차이가 나게 되고, 이에 의해 솔더 볼에 열적 응력이 매우 심하게 인가된다. 그러므로, 솔더 볼은 이러한 열적 응력에 견딜 수 있는 강도를 가져야 하는데, 전술된 바와 같이 솔더 볼이 마운트되는 금속 패턴의 지지 구조가 매우 취약하기 때문에, 솔더 볼에 열적 응력에 의한 균열이 쉽게 발생되는 문제점이 있다. 뿐만 아니라, 지지 구조가 취약한 금속 패턴과 절연층 사이에서도 균열이 쉽게 발생된다.Also, as is well known, the thermal expansion coefficient difference between the semiconductor chip and the board on which the package is mounted is very large. Therefore, the degree of expansion and contraction of the semiconductor chip and the board is greatly different, whereby thermal stress is very severely applied to the solder ball. Therefore, the solder ball must have a strength that can withstand such thermal stress. As described above, since the support structure of the metal pattern on which the solder ball is mounted is very weak, the solder ball is easily cracked due to thermal stress. There is this. In addition, cracking easily occurs between the metal pattern and the insulating layer having a weak supporting structure.
또한, 종래의 패키지에서는 본드 패드와 금속 패턴간의 거리가 너무 인접하여, 전기적 특성에 문제가 많다. 물론, 절연층의 두께를 두껍게 하면 상기된 문제가 해소되나, 절연층의 두께를 너무 두껍게 형성하게 되면, 금속 패턴이 깊은 식각홈을 통해 본드 패드에 정확하게 연결되기가 곤란하다는 새로운 문제점이 유발된다. 그러므로, 절연층의 두께를 두껍게 하는데는 한계가 있다.In addition, in the conventional package, the distance between the bond pad and the metal pattern is too close, and there are many problems in electrical characteristics. Of course, if the thickness of the insulating layer is thickened, the above-mentioned problem is solved. However, if the thickness of the insulating layer is formed too thick, a new problem arises that it is difficult to accurately connect the metal pattern to the bond pad through the deep etching groove. Therefore, there is a limit to increasing the thickness of the insulating layer.
따라서, 본 발명은 종래의 웨이퍼 레벨 패키지가 안고 있는 문제점을 해소하기 위해 안출된 것으로서, 금속 패턴 사용을 배제하고 대신에 지지 구조가 대폭 강화되는 다른 접속 매개체를 사용하므로써, 솔더 볼의 접합 강도를 대폭 강화시킬 수 있는 웨이퍼 레벨 패키지를 제공하는데 목적이 있다.Accordingly, the present invention has been made to solve the problems of the conventional wafer level package, and by using other connection media, which eliminates the use of metal patterns and greatly strengthens the support structure, the bonding strength of the solder balls can be greatly improved. The objective is to provide a wafer level package that can be enhanced.
본 발명의 다른 목적은, 접속 매개체와 반도체 칩의 본드 패드간의 거리를 충분히 이격되도록 하여, 패키지의 전기적 특성을 향상시키는데 있다.Another object of the present invention is to improve the electrical characteristics of a package by sufficiently separating the distance between the connection medium and the bond pad of the semiconductor chip.
도 1 내지 도 3은 종래의 웨이퍼 레벨 패키지의 3가지 유형을 나타낸 단면도.1 to 3 are cross-sectional views illustrating three types of conventional wafer level packages.
도 4 내지 도 9는 본 발명에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 도면.4-9 illustrate wafer level packages according to the present invention in the order of manufacturing process.
도 10은 도 9에 도시된 웨이퍼 레벨 패키지의 다른 변형예를 나타낸 단면도.FIG. 10 is a sectional view of another modification of the wafer level package shown in FIG. 9; FIG.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
10 ; 웨이퍼 11 ; 본드 패드10; Wafer 11; Bond pad
20 ; 패턴 필름 21 ; 금속층20; Pattern film 21; Metal layer
22,23 ; 절연층 24 ; 접착층22,23; Insulating layer 24; Adhesive layer
25 ; 식각홈 26 ; 단차면25; Etching grooves 26; Step surface
30 ; 금속 와이어 40 ; 솔더 볼30; Metal wire 40; Solder ball
50 ; 봉지제50; Encapsulant
상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 웨이퍼 레벨 패키지는다음과 같은 구성으로 이루어진다.In order to achieve the above object, the wafer level package according to the present invention has the following configuration.
본드 패드가 배치된 반도체 칩의 표면에 패턴 필름이 접착된다. 패턴 필름에는 본드 패드를 노출시키는 개구부가 형성되고, 개구부의 양측벽에는 와이어 본딩을 위한 단차면이 형성된다. 단차면에는 패턴 필름에 내장된 금속층이 배열된다. 본드 패드와 패턴 필름의 단차면에 배열된 금속층이 금속 와이어에 의해 전기적으로 연결된다. 패턴 필름상에는 솔더 볼이 마운트되고, 실장 가능한 정도인 솔더 볼의 일부가 노출되도록 반도체 칩 상부가 봉지제로 봉지된다.The pattern film is adhere | attached on the surface of the semiconductor chip in which the bond pad was arrange | positioned. An opening for exposing the bond pad is formed in the pattern film, and a stepped surface for wire bonding is formed on both side walls of the opening. On the stepped surface, the metal layer embedded in the pattern film is arranged. The metal layer arranged on the step surface of the bond pad and the pattern film is electrically connected by the metal wire. The solder ball is mounted on the pattern film, and the upper part of the semiconductor chip is sealed with an encapsulant so that a part of the solder ball which can be mounted is exposed.
상기된 본 발명의 구성에 의하면, 금속 패턴 대신에 패턴 필름이 사용되고, 이 패턴 필름은 두께 조절이 용이한 접착제를 매개로 반도체 칩이 접착되며, 아울러 패턴 필름은 금속 와이어에 의해 연결되므로, 본드 패드와의 전기적 접속은 확실하게 보장되면서 패턴 필름과 본드 패드간의 거리를 충분히 이격시킬 수가 있게 된다. 따라서, 패키지의 전기적 특성이 향상된다. 또한, 패턴 필름은 그 내부에 금속층이 일체로 배열된 구조이므로, 이러한 금속 패턴에 마운트된 솔더 볼의 접합 강도가 강화된다.According to the above-described configuration of the present invention, a pattern film is used instead of a metal pattern, and the pattern film is bonded to a semiconductor chip through an adhesive whose thickness can be easily adjusted, and the pattern film is connected by a metal wire, so that a bond pad The electrical connection with is securely ensured and the distance between the pattern film and the bond pad can be sufficiently separated. Thus, the electrical characteristics of the package are improved. In addition, since the pattern film has a structure in which metal layers are integrally arranged therein, the bonding strength of the solder balls mounted on the metal pattern is enhanced.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.
도 4 내지 도 9는 본 발명에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 도면이다.4 through 9 illustrate wafer level packages according to the present invention in the order of manufacturing process.
먼저, 웨이퍼(10)에는 복수개의 반도체 칩이 구성되어 있고, 각 반도체 칩의 본드 패드는 웨이퍼(10) 표면에 배치되어 있다. 이러한 웨이퍼(10) 표면에 도 4와 같이 패턴 필름(20)을 접착한다.First, a plurality of semiconductor chips are formed on the wafer 10, and bond pads of the semiconductor chips are arranged on the surface of the wafer 10. The pattern film 20 is adhered to the surface of the wafer 10 as shown in FIG. 4.
패턴 필름(20)의 내부 구조가 도 5에 상세하게 도시되어 있다. 도 5에 도시된 바와 같이, 패턴 필름(20)은 금속층(21)의 상하면에 절연층(22,23)이 맞대어지고, 하부 절연층(23)의 밑면에 접착층(24)이 위치한 구조를 갖는다. 따라서, 패턴 필름(20)의 금속층(21)과 본드 패드(11)간의 거리는 접착층(24)의 두께를 조절하는 것에 의해서 충분히 이격시킬 수가 있게 된다.The internal structure of the pattern film 20 is shown in detail in FIG. 5. As shown in FIG. 5, the pattern film 20 has a structure in which the insulating layers 22 and 23 abut on the upper and lower surfaces of the metal layer 21, and the adhesive layer 24 is disposed on the bottom surface of the lower insulating layer 23. . Accordingly, the distance between the metal layer 21 and the bond pad 11 of the pattern film 20 can be sufficiently separated by adjusting the thickness of the adhesive layer 24.
계속해서, 도 6에 도시된 바와 같이, 패턴 필름(20)을 식각하여 식각홈(25)을 형성하고, 이 식각홈(25)을 통해 도 7과 같이 본드 패드(11)를 노출시킨다. 또한, 식각홈(25)의 양측벽에는 금속층(21)이 노출되는 단차면(26)을 형성한다.Subsequently, as shown in FIG. 6, the pattern film 20 is etched to form an etch groove 25, and the bond pad 11 is exposed through the etch groove 25 as shown in FIG. 7. In addition, on both side walls of the etching groove 25, a stepped surface 26 through which the metal layer 21 is exposed is formed.
이어서, 도 8과 같이, 금속 와이어(30)로 단차면(26)상에 배열된 금속층(21)과 본드 패드(11)를 전기적으로 연결한다. 그런 다음, 상부 절연층(22)으로부터 노출된 금속층(21) 부분, 즉 볼 랜드에 솔더 볼(40)을 마운트한다.Subsequently, as shown in FIG. 8, the metal layer 21 and the bond pad 11 arranged on the step surface 26 are electrically connected with the metal wire 30. Then, the solder balls 40 are mounted on portions of the metal layer 21 exposed from the upper insulating layer 22, that is, the ball lands.
마지막으로, 실장 가능한 정도인 솔더 볼(40)의 일부분이 노출되도록, 웨이퍼(10) 상부를 봉지제(50)로 봉지하고, 스크라이브 라인을 따라 웨이퍼(10)를 절단하면, 도 9에 도시된 본 발명에 따른 웨이퍼 레벨 패키지가 완성된다.Finally, when the upper portion of the wafer 10 is sealed with the encapsulant 50 and the wafer 10 is cut along the scribe line so that a portion of the solder ball 40 that is mountable is exposed, the wafer 10 is shown in FIG. 9. The wafer level package according to the invention is completed.
한편, 도 9에서 솔더 볼(40)은 전체가 봉지제(50)로부터 노출된 상태가 아니므로, 실장 면적을 확장하기 위해서 도 10에 도시된 바와 같이 다른 솔더 볼(41)을 일부 노출된 솔더 볼(40)상에 별도로 형성할 수도 있다.Meanwhile, in FIG. 9, since the solder ball 40 is not entirely exposed from the encapsulant 50, the solder ball 40 partially exposed the other solder balls 41 as shown in FIG. 10 to expand the mounting area. It may be formed separately on the ball (40).
이상에서 설명한 바와 같이 본 발명에 의하면, 금속 패턴 대신에 패턴 필름이 사용되고, 이 패턴 필름은 두께 조절이 용이한 접착제를 매개로 반도체 칩이 접착되며, 아울러 패턴 필름은 금속 와이어에 의해 연결되므로, 본드 패드와의 전기적 접속은 확실하게 보장되면서 패턴 필름과 본드 패드간의 거리를 충분히 이격시킬 수가 있게 된다. 따라서, 패키지의 전기적 특성이 향상된다.As described above, according to the present invention, a pattern film is used instead of a metal pattern, and the pattern film is bonded to a semiconductor chip through an adhesive which can be easily adjusted in thickness, and the pattern film is connected by a metal wire, thereby bonding The electrical connection with the pads can be securely ensured and the distance between the pattern film and the bond pads can be sufficiently separated. Thus, the electrical characteristics of the package are improved.
또한, 패턴 필름은 그 내부에 금속층이 일체로 배열된 구조이므로, 이러한 금속 패턴에 마운트된 솔더 볼의 접합 강도가 강화된다.In addition, since the pattern film has a structure in which metal layers are integrally arranged therein, the bonding strength of the solder balls mounted on the metal pattern is enhanced.
이상에서는 본 발명의 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990064334A KR20010061792A (en) | 1999-12-29 | 1999-12-29 | Wafer level package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990064334A KR20010061792A (en) | 1999-12-29 | 1999-12-29 | Wafer level package |
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| Publication Number | Publication Date |
|---|---|
| KR20010061792A true KR20010061792A (en) | 2001-07-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990064334A KR20010061792A (en) | 1999-12-29 | 1999-12-29 | Wafer level package |
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| Country | Link |
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| KR (1) | KR20010061792A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100432137B1 (en) * | 2001-09-20 | 2004-05-17 | 동부전자 주식회사 | Chip scale package fabrication method |
-
1999
- 1999-12-29 KR KR1019990064334A patent/KR20010061792A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100432137B1 (en) * | 2001-09-20 | 2004-05-17 | 동부전자 주식회사 | Chip scale package fabrication method |
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