JP2008181585A - 基準電圧発生回路及び半導体集積回路装置 - Google Patents
基準電圧発生回路及び半導体集積回路装置 Download PDFInfo
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- JP2008181585A JP2008181585A JP2007013178A JP2007013178A JP2008181585A JP 2008181585 A JP2008181585 A JP 2008181585A JP 2007013178 A JP2007013178 A JP 2007013178A JP 2007013178 A JP2007013178 A JP 2007013178A JP 2008181585 A JP2008181585 A JP 2008181585A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4099—Dummy cell treatment; Reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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- Semiconductor Integrated Circuits (AREA)
- Control Of Electrical Variables (AREA)
Abstract
【解決手段】本発明の基準電圧発生回路は、低VtPMOSトランジスタLPと低VtNMOSトランジスタLNと所定の抵抗値を有する抵抗Rとを直列接続して構成され、一端に基準電圧VCLRを発生するモニタ回路20を備えている。モニタ回路20にはモニタ電流IRが供給され、その他端(ノードND5)が定電圧VFQに制御される。プロセスばらつきに応じて変化するモニタ電流IRに基づき、基準電圧VCLRの電圧値が所定の中心電圧値からプロセスばらつきに応じた範囲内で補正される。これにより、基準電圧VCLRに基づく電源電圧を供給される低Vtトランジスタを含む回路の遅延時間のばらつきを小さくすることができる。
【選択図】図3
Description
12、13…基準電圧発生回路
14…VLNG/VBDR発生回路
15…VF発生回路
16…VCL発生回路
21…定電圧発生部
22…温度依存バイアス部
23a、23b…レベル変換回路
P10〜P15、P20〜P25…PMOSトランジスタ
N10〜N15、N20〜N25…NMOSトランジスタ
ST1、ST2…スイッチトランジスタ
R、R1、R2、R3…抵抗
IS…定電流源
VCLR…基準電圧
VCL…内部電源電圧
VDDR…電源電圧
VDD…外部電源電圧
VLNG、VBDR、VF、VF1、VF2…定電圧
IR…モニタ電流
ND1〜ND6、ND11、ND12…ノード
Claims (9)
- 低しきい値PMOSトランジスタと低しきい値NMOSトランジスタと所定の抵抗値を有する抵抗とを直列接続して構成され、一端に基準電圧を発生するモニタ回路と、
前記モニタ回路にモニタ電流を供給するとともに、前記モニタ回路の他端を定電圧に制御する付加回路と、
を備え、プロセスばらつきに応じて変化する前記モニタ電流に基づき、前記基準電圧の電圧値が所定の中心電圧値から前記プロセスばらつきに応じた範囲内で補正されることを特徴とする基準電圧発生回路。 - 前記低しきい値PMOSトランジスタ及び前記低しきい値NMOSトランジスタは、前記プロセスばらつきにより動作遅延が大きくなる場合は前記基準電圧が所定量だけ増加し、前記プロセスばらつきにより動作遅延が小さくなる場合は前記基準電圧が所定量だけ減少するようにそれぞれのサイズが予め調整されていることを特徴とする請求項1に記載の基準電圧発生回路。
- 前記低しきい値PMOSトランジスタ及び前記低しきい値NMOSトランジスタは、互いのゲート及びドレインが共通接続されることを特徴とする請求項2に記載の基準電圧発生回路。
- 低しきい値MOSトランジスタを含んで構成され、内部電源電圧が供給される内部回路と、
所定の温度範囲内で温度を検知する温度センサ回路と、
前記内部電源電圧の基準となる基準電圧を発生し、前記温度センサ回路により検知される温度に対応してそれぞれ調整された複数の基準電圧発生回路と、
を備え、
前記複数の基準電圧発生回路の各々は、
低しきい値PMOSトランジスタと低しきい値NMOSトランジスタと所定の抵抗値を有する抵抗とを直列接続して構成され、一端に前記基準電圧を発生するモニタ回路と、
前記モニタ回路にモニタ電流を供給するとともに、前記モニタ回路の他端を定電圧に制御する付加回路と、
を含み、前記基準電圧発生回路は、プロセスばらつきに応じて変化する前記モニタ電流に基づき、前記基準電圧の電圧値が所定の中心電圧値から前記プロセスばらつきに応じた範囲内で補正されることを特徴とする半導体集積回路装置。 - 前記温度センサ回路は、所定の温度を境界に2値で温度を検知し、
低温側の温度に対応して調整された第1の前記基準電圧発生回路と、高温側の温度に対応して調整された第2の前記基準電圧発生回路と、が設けられ、
前記温度センサ回路により低温側の温度が検知されたときは前記第1の基準電圧発生回路を動作させ、前記温度センサ回路により高温側の温度が検知されたときは前記第2の基準電圧発生回路を動作させることを特徴とする請求項4に記載の半導体集積回路装置。 - 前記第1の基準電圧発生回路及び前記第2の基準電圧発生回路は、前記低しきい値PMOSトランジスタ及び前記低しきい値NMOSトランジスタのそれぞれのサイズと、前記抵抗の抵抗値に基づいて予め調整されていることを特徴とする請求項5に記載の半導体集積回路装置。
- 前記低しきい値PMOSトランジスタ及び前記低しきい値NMOSトランジスタは、前記プロセスばらつきにより動作遅延が大きくなる場合は前記基準電圧が所定量だけ増加し、前記プロセスばらつきにより動作遅延が小さくなる場合は前記基準電圧が所定量だけ減少するようにそれぞれのサイズが予め調整されていることを特徴とする請求項6に記載の半導体集積回路装置。
- 前記内部回路は、前記低しきい値MOSトランジスタを含んで構成され前記内部電源電圧を供給されるディレイ回路を含むことを特徴とする請求項5に記載の半導体集積回路装置。
- データを記憶するメモリ回路を更に備え、前記内部回路は、前記メモリ回路へのアクセスパスを構成する回路であることを特徴とする請求項5に記載の半導体集積回路装置。
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JP2007013178A JP4524688B2 (ja) | 2007-01-23 | 2007-01-23 | 基準電圧発生回路及び半導体集積回路装置 |
US12/018,375 US7642843B2 (en) | 2007-01-23 | 2008-01-23 | Reference voltage generating circuit and semiconductor integrated circuit device |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20100075394A (ko) * | 2008-12-24 | 2010-07-02 | 세이코 인스트루 가부시키가이샤 | 기준 전압 회로 |
JP2012099065A (ja) * | 2010-11-05 | 2012-05-24 | Handotai Rikougaku Kenkyu Center:Kk | 基準電圧源回路 |
JP2015195393A (ja) * | 2009-07-28 | 2015-11-05 | スカイワークス ソリューションズ, インコーポレイテッドSkyworks Solutions, Inc. | 半導体プロセスセンサおよび半導体プロセスを特徴付ける方法 |
KR102397443B1 (ko) * | 2021-01-06 | 2022-05-12 | 평택대학교 산학협력단 | 프로세스 및 온도 변화에 따라 변경되는 전압을 제공하는 집적 회로 |
Families Citing this family (13)
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JP2010219486A (ja) * | 2009-03-19 | 2010-09-30 | Renesas Electronics Corp | 中間電位発生回路 |
JP2010283117A (ja) * | 2009-06-04 | 2010-12-16 | Renesas Electronics Corp | 半導体装置及び半導体装置の動作方法 |
US8786355B2 (en) * | 2011-11-10 | 2014-07-22 | Qualcomm Incorporated | Low-power voltage reference circuit |
KR20140023749A (ko) * | 2012-08-17 | 2014-02-27 | 에스케이하이닉스 주식회사 | 반도체 장치의 기준 전압 발생 회로 |
CN104464824B (zh) * | 2013-09-17 | 2017-12-01 | 中芯国际集成电路制造(北京)有限公司 | 存储阵列中的mos管阈值电压的测试方法 |
US11515871B2 (en) * | 2020-05-25 | 2022-11-29 | Mavagail Technology, LLC | Temperature sensor circuits for integrated circuit devices |
KR20220027550A (ko) * | 2020-08-27 | 2022-03-08 | 삼성전자주식회사 | 온도 보상을 수행하는 메모리 장치 및 그 동작방법 |
EP4033312A4 (en) | 2020-11-25 | 2022-10-12 | Changxin Memory Technologies, Inc. | CONTROL CIRCUIT AND DELAY CIRCUIT |
EP4033661B1 (en) | 2020-11-25 | 2024-01-24 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
CN114553196A (zh) * | 2020-11-25 | 2022-05-27 | 长鑫存储技术有限公司 | 电位产生电路、反相器、延时电路和逻辑门电路 |
US11681313B2 (en) | 2020-11-25 | 2023-06-20 | Changxin Memory Technologies, Inc. | Voltage generating circuit, inverter, delay circuit, and logic gate circuit |
EP4033664B1 (en) | 2020-11-25 | 2024-01-10 | Changxin Memory Technologies, Inc. | Potential generation circuit, inverter, delay circuit, and logic gate circuit |
US11605427B2 (en) * | 2021-01-04 | 2023-03-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Memory device with write pulse trimming |
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JPH01302849A (ja) * | 1988-05-31 | 1989-12-06 | Fujitsu Ltd | 半導体集積回路装置 |
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KR20100075394A (ko) * | 2008-12-24 | 2010-07-02 | 세이코 인스트루 가부시키가이샤 | 기준 전압 회로 |
KR101653000B1 (ko) | 2008-12-24 | 2016-08-31 | 에스아이아이 세미컨덕터 가부시키가이샤 | 기준 전압 회로 |
JP2015195393A (ja) * | 2009-07-28 | 2015-11-05 | スカイワークス ソリューションズ, インコーポレイテッドSkyworks Solutions, Inc. | 半導体プロセスセンサおよび半導体プロセスを特徴付ける方法 |
JP2012099065A (ja) * | 2010-11-05 | 2012-05-24 | Handotai Rikougaku Kenkyu Center:Kk | 基準電圧源回路 |
KR102397443B1 (ko) * | 2021-01-06 | 2022-05-12 | 평택대학교 산학협력단 | 프로세스 및 온도 변화에 따라 변경되는 전압을 제공하는 집적 회로 |
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