JP2008159736A - 半導体装置及びその電源供給方法 - Google Patents
半導体装置及びその電源供給方法 Download PDFInfo
- Publication number
- JP2008159736A JP2008159736A JP2006345439A JP2006345439A JP2008159736A JP 2008159736 A JP2008159736 A JP 2008159736A JP 2006345439 A JP2006345439 A JP 2006345439A JP 2006345439 A JP2006345439 A JP 2006345439A JP 2008159736 A JP2008159736 A JP 2008159736A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- voltage
- semiconductor device
- supplied
- predetermined operating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】 半導体装置を構成するn個の内部構成部品の低位側及び高位側電源配線を接地電圧GNDと電源VDD間に順に直列接続する。構成部品の所定動作電圧を加算した電圧を中間電源及び電源として供給し、構成部品の低位側及び高位側電源の差電圧を所定動作電圧となるようにする。本発明の電源供給方法によれば、半導体装置に流れる電流は1/n、電源電圧の電圧降下を1/nに低減でき、電力の供給が容易となる半導体装置が得られる。
【選択図】 図5
Description
1−A、1−B、1−C、1−D 内部回路領域
10 マルチチップパッケージ半導体装置
10−A、10−B、10−C、10−D 半導体チップ
20、30 積層型半導体装置
20−A、20−B、20−C、20−D、30−A、30−B、30−C、30−D 貫通電極を備えた半導体チップ
21、31 内部回路
Claims (8)
- 複数の構成部品からなる半導体装置において、前記複数の構成部品の低位側及び高位側電源配線を接地電圧と第1の電源間に順に直列接続し、それぞれの構成部品の電源電圧が所定動作電圧となるように、それぞれの構成部品の所定動作電圧を加算した電圧を供給することを特徴とする半導体装置。
- 前記複数の構成部品の低位側電源電圧と高位側電源電圧とを供給する配線間に、それぞれ静電容量を設けたことを特徴とする請求項1に記載の半導体装置。
- 前記半導体装置は1つの半導体チップから構成され、内部回路を同等の電力を消費するn個(nは2以上の自然数)の内部回路領域に分割し、それぞれの内部回路領域の低位側電源電圧として、接地電圧、所定動作電圧の1倍、2倍、・・、(n―1)倍の電圧を、高位側電源電圧として所定動作電圧の1倍、2倍、・・、(n―1)倍、n倍の電圧を供給し、それぞれの内部回路領域に前記所定動作電圧を供給することを特徴とする請求項1に記載の半導体装置。
- 前記半導体装置は複数の半導体チップを構成部品としたマルチチップパッケージ半導体装置であり、接地電圧側から電源側へ順に、それぞれの半導体チップの所定動作電圧を加算した電圧を供給し、それぞれの半導体チップに所定動作電圧を供給することを特徴とする請求項1に記載の半導体装置。
- 前記半導体装置は同じ構成のn個(nは2以上の自然数)の半導体チップを構成部品としたマルチチップパッケージ半導体装置であり、それぞれの半導体チップの低位側電源電圧として、接地電圧、所定動作電圧の1倍、2倍、・・、(n―1)倍の電圧を、高位側電源電圧として所定動作電圧の1倍、2倍、・・、(n―1)倍、n倍の電圧を供給し、それぞれの半導体チップに所定動作電圧を供給することを特徴とする請求項1に記載の半導体装置。
- 前記半導体装置は貫通電極を備えた複数の半導体チップを構成部品とした積層型半導体装置であり、接地電圧側から電源側へ順に、それぞれの半導体チップの所定動作電圧を加算した電圧を供給し、それぞれの半導体チップに所定動作電圧を供給することを特徴とする請求項1に記載の半導体装置。
- 前記半導体装置は同じ構成の貫通電極を備えたn個(nは2以上の自然数)の半導体チップを構成部品とした積層型半導体装置であり、それぞれの半導体チップの低位側電源電圧として、接地電圧、所定動作電圧の1倍、2倍、・・、(n―1)倍の電圧を、高位側電源電圧として所定動作電圧の1倍、2倍、・・、(n―1)倍、n倍の電圧を供給し、それぞれの半導体チップに所定動作電圧を供給することを特徴とする請求項1に記載の半導体装置。
- 複数の構成部品からなる半導体装置の電源供給方法において、前記複数の構成部品の低位側及び高位側電源配線を接地電圧と電源間に順に直列接続し、それぞれの構成部品の電源電圧が所定動作電圧となるように、接地電圧側から電源側へ、直列接続された構成部品のそれぞれの所定動作電圧を加算した電圧を供給することを特徴とする半導体装置の電源供給方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006345439A JP2008159736A (ja) | 2006-12-22 | 2006-12-22 | 半導体装置及びその電源供給方法 |
US12/000,884 US20080150359A1 (en) | 2006-12-22 | 2007-12-18 | Semiconductor device and power supply for the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006345439A JP2008159736A (ja) | 2006-12-22 | 2006-12-22 | 半導体装置及びその電源供給方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008159736A true JP2008159736A (ja) | 2008-07-10 |
Family
ID=39541779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006345439A Pending JP2008159736A (ja) | 2006-12-22 | 2006-12-22 | 半導体装置及びその電源供給方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20080150359A1 (ja) |
JP (1) | JP2008159736A (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010109264A (ja) * | 2008-10-31 | 2010-05-13 | Hitachi Ltd | 半導体集積回路装置 |
US8587117B2 (en) | 2011-04-25 | 2013-11-19 | Elpida Memory, Inc. | Stacked semiconductor chips having circuit element provided with each of the semiconductor chips |
JP2014107543A (ja) * | 2012-11-22 | 2014-06-09 | Soongsil Univ Research Consortium Techno-Park | 積層構造を有する集積回路 |
JP2015163433A (ja) * | 2014-02-28 | 2015-09-10 | キヤノン株式会社 | 記録装置及び記録ヘッド |
WO2018055814A1 (ja) * | 2016-09-23 | 2018-03-29 | 東芝メモリ株式会社 | メモリデバイス |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20110004649A (ko) * | 2009-07-08 | 2011-01-14 | 삼성전자주식회사 | 멀티칩 시스템 |
KR102498883B1 (ko) * | 2018-01-31 | 2023-02-13 | 삼성전자주식회사 | 전류를 분산시키는 관통 전극들을 포함하는 반도체 장치 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5079441A (en) * | 1988-12-19 | 1992-01-07 | Texas Instruments Incorporated | Integrated circuit having an internal reference circuit to supply internal logic circuits with a reduced voltage |
US5381330A (en) * | 1993-09-08 | 1995-01-10 | Grundl & Hoffmann | Half-bridge arrangement for switching electrical power |
JP3300593B2 (ja) * | 1995-06-15 | 2002-07-08 | 株式会社東芝 | 半導体集積回路装置 |
US5856918A (en) * | 1995-11-08 | 1999-01-05 | Sony Corporation | Internal power supply circuit |
JP3517154B2 (ja) * | 1998-04-30 | 2004-04-05 | 株式会社東芝 | 誘電体分離集積回路 |
JP2001110184A (ja) * | 1999-10-14 | 2001-04-20 | Hitachi Ltd | 半導体装置 |
JP4748867B2 (ja) * | 2001-03-05 | 2011-08-17 | パナソニック株式会社 | 集積回路装置 |
US6635970B2 (en) * | 2002-02-06 | 2003-10-21 | International Business Machines Corporation | Power distribution design method for stacked flip-chip packages |
US6861894B2 (en) * | 2002-09-27 | 2005-03-01 | Sandisk Corporation | Charge pump with Fibonacci number multiplication |
US7239193B2 (en) * | 2003-12-25 | 2007-07-03 | Kabushiki Kaisha Toshiba | Semiconductor device |
TWI298828B (en) * | 2005-06-29 | 2008-07-11 | Novatek Microelectronics Corp | Charge pump for generating arbitrary voltage level |
-
2006
- 2006-12-22 JP JP2006345439A patent/JP2008159736A/ja active Pending
-
2007
- 2007-12-18 US US12/000,884 patent/US20080150359A1/en not_active Abandoned
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010109264A (ja) * | 2008-10-31 | 2010-05-13 | Hitachi Ltd | 半導体集積回路装置 |
US8587117B2 (en) | 2011-04-25 | 2013-11-19 | Elpida Memory, Inc. | Stacked semiconductor chips having circuit element provided with each of the semiconductor chips |
JP2014107543A (ja) * | 2012-11-22 | 2014-06-09 | Soongsil Univ Research Consortium Techno-Park | 積層構造を有する集積回路 |
JP2015163433A (ja) * | 2014-02-28 | 2015-09-10 | キヤノン株式会社 | 記録装置及び記録ヘッド |
WO2018055814A1 (ja) * | 2016-09-23 | 2018-03-29 | 東芝メモリ株式会社 | メモリデバイス |
WO2018055734A1 (ja) * | 2016-09-23 | 2018-03-29 | 東芝メモリ株式会社 | メモリデバイス |
JPWO2018055814A1 (ja) * | 2016-09-23 | 2019-04-25 | 東芝メモリ株式会社 | メモリデバイス |
JPWO2018055734A1 (ja) * | 2016-09-23 | 2019-06-24 | 東芝メモリ株式会社 | メモリデバイス |
TWI698976B (zh) * | 2016-09-23 | 2020-07-11 | 日商東芝記憶體股份有限公司 | 記憶體裝置 |
US10790266B2 (en) | 2016-09-23 | 2020-09-29 | Toshiba Memory Corporation | Memory device with a plurality of stacked memory core chips |
US10811393B2 (en) | 2016-09-23 | 2020-10-20 | Toshiba Memory Corporation | Memory device |
US11270981B2 (en) | 2016-09-23 | 2022-03-08 | Kioxia Corporation | Memory device |
Also Published As
Publication number | Publication date |
---|---|
US20080150359A1 (en) | 2008-06-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9479154B2 (en) | Semiconductor integrated circuit | |
US7411267B2 (en) | Semiconductor integrated circuit device | |
JP2008159736A (ja) | 半導体装置及びその電源供給方法 | |
US8451050B2 (en) | Information technology equipment | |
JP2006121654A (ja) | レベル変換回路 | |
JP2008053319A (ja) | 半導体装置 | |
JP5312849B2 (ja) | 集積回路 | |
JP2008028004A (ja) | 半導体装置 | |
WO2015083289A1 (ja) | 半導体装置 | |
US8928513B1 (en) | Current steering digital-to-analog converter (DAC) switch driver | |
US6946876B2 (en) | Semiconductor integrated circuit device and electronic system | |
CN107112280B (zh) | 半导体集成电路装置 | |
JP2006121377A (ja) | 入力回路及び半導体装置 | |
JP3730003B2 (ja) | 半導体装置 | |
JP2006319267A (ja) | 半導体集積回路 | |
US20090284287A1 (en) | Output buffer circuit and integrated circuit | |
US20110102954A1 (en) | Semiconductor integrated circuit | |
JP2006166384A (ja) | 二重絶縁ゲート電界トランジスタを用いたmosトランジスタ回路およびそれを用いたcmosトランジスタ回路、sramセル回路、cmos−sramセル回路、集積回路 | |
JP5254596B2 (ja) | 半導体集積回路および電子回路 | |
KR101211683B1 (ko) | 반도체 집적회로 | |
US8829970B2 (en) | Standard cell circuit, semiconductor integrated circuit, and semiconductor integrated circuit device | |
JP2010245413A (ja) | 半導体集積回路装置 | |
WO2023127218A1 (ja) | 電源装置 | |
JP2007027401A (ja) | 半導体装置 | |
JP2008011242A (ja) | 駆動回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090227 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090311 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090507 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090617 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20091021 |