JP2008072716A - プログラマブルロジックデバイス用のデジタル適応回路網および方法 - Google Patents

プログラマブルロジックデバイス用のデジタル適応回路網および方法 Download PDF

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Publication number
JP2008072716A
JP2008072716A JP2007237202A JP2007237202A JP2008072716A JP 2008072716 A JP2008072716 A JP 2008072716A JP 2007237202 A JP2007237202 A JP 2007237202A JP 2007237202 A JP2007237202 A JP 2007237202A JP 2008072716 A JP2008072716 A JP 2008072716A
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Japan
Prior art keywords
equalization
transition
data
consecutive
value
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JP2007237202A
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English (en)
Japanese (ja)
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JP2008072716A5 (enExample
Inventor
Wilson Wong
ウォン ウィルソン
Doris Po Ching Chan
ポ チン チャン ドリス
Sergey Shumarayev
シュマライェブ セルゲイ
Simardeep Maangat
マーンガット シマーディープ
Tim Tri Hoang
トリ ホアン ティム
Tin H Lai
エイチ． レイ ティン
Thungoc M Tran
エム． トラン サンゴック
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Altera Corp
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Altera Corp
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Application filed by Altera Corp filed Critical Altera Corp
Publication of JP2008072716A publication Critical patent/JP2008072716A/ja
Publication of JP2008072716A5 publication Critical patent/JP2008072716A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H04L25/03885—Line equalisers; line build-out devices adaptive

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2007237202A 2006-09-14 2007-09-12 プログラマブルロジックデバイス用のデジタル適応回路網および方法 Pending JP2008072716A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/522,284 US7920621B2 (en) 2006-09-14 2006-09-14 Digital adaptation circuitry and methods for programmable logic devices

Related Child Applications (1)

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JP2010291281A Division JP5291699B2 (ja) 2006-09-14 2010-12-27 プログラマブルロジックデバイス用のデジタル適応回路網および方法

Publications (2)

Publication Number Publication Date
JP2008072716A true JP2008072716A (ja) 2008-03-27
JP2008072716A5 JP2008072716A5 (enExample) 2010-10-14

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Application Number Title Priority Date Filing Date
JP2007237202A Pending JP2008072716A (ja) 2006-09-14 2007-09-12 プログラマブルロジックデバイス用のデジタル適応回路網および方法
JP2010291281A Expired - Fee Related JP5291699B2 (ja) 2006-09-14 2010-12-27 プログラマブルロジックデバイス用のデジタル適応回路網および方法
JP2011100172A Pending JP2011193505A (ja) 2006-09-14 2011-04-27 プログラマブルロジックデバイス用のデジタル適応回路網および方法
JP2013268773A Expired - Fee Related JP5889272B2 (ja) 2006-09-14 2013-12-26 プログラマブルロジックデバイス用のデジタル適応回路網および方法

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JP2010291281A Expired - Fee Related JP5291699B2 (ja) 2006-09-14 2010-12-27 プログラマブルロジックデバイス用のデジタル適応回路網および方法
JP2011100172A Pending JP2011193505A (ja) 2006-09-14 2011-04-27 プログラマブルロジックデバイス用のデジタル適応回路網および方法
JP2013268773A Expired - Fee Related JP5889272B2 (ja) 2006-09-14 2013-12-26 プログラマブルロジックデバイス用のデジタル適応回路網および方法

Country Status (4)

Country Link
US (2) US7920621B2 (enExample)
EP (1) EP1901507A1 (enExample)
JP (4) JP2008072716A (enExample)
CN (1) CN101145775A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2008105070A1 (ja) * 2007-02-27 2010-06-03 富士通株式会社 適応等化回路
JP2012170079A (ja) * 2011-02-14 2012-09-06 Fujitsu Ltd 適応位相等化のためのシステム及び方法
JP2014039292A (ja) * 2007-04-09 2014-02-27 Silicon Image Inc シリアル通信リンクのクロック・データ再生回路と使用する適応等化器

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GB0504425D0 (en) * 2005-03-03 2005-04-06 Texas Instruments Ltd Equalisation circuit
US8477834B2 (en) 2006-11-16 2013-07-02 Rambus, Inc. Partial response decision-feedback equalization with adaptation based on edge samples
US7782088B1 (en) * 2007-02-15 2010-08-24 Altera Corporation Sharing adaptive dispersion compensation engine among programmable logic device serial interface channels
US8208528B1 (en) * 2007-12-13 2012-06-26 Altera Corporation Programmable adaptation convergence detection
US8369470B2 (en) * 2008-11-25 2013-02-05 Agere Systems, LLC Methods and apparatus for adapting one or more equalization parameters by reducing group delay spread
US8484518B2 (en) * 2009-04-28 2013-07-09 Alcatel Lucent System and method for consecutive identical digit reduction
US8063807B1 (en) 2009-04-30 2011-11-22 Altera Corporation Equalization circuitry including a digital-to-analog converter having a voltage divider and a multiplexer
US8707244B1 (en) 2010-08-20 2014-04-22 Altera Corporation Methods and systems for performing signal activity extraction
US8705605B1 (en) 2011-11-03 2014-04-22 Altera Corporation Technique for providing loopback testing with single stage equalizer
CN102664842A (zh) * 2012-03-08 2012-09-12 无锡华大国奇科技有限公司 一种减小高速信号传输码间干扰的系统
TW201404105A (zh) * 2012-07-06 2014-01-16 Novatek Microelectronics Corp 時脈資料回復電路及方法
CN103546403A (zh) * 2012-07-11 2014-01-29 联咏科技股份有限公司 时钟数据回复电路及方法
CN112019225B (zh) * 2020-08-27 2022-07-05 群联电子股份有限公司 信号接收电路、存储器存储装置及均衡器电路的校准方法
US11303484B1 (en) * 2021-04-02 2022-04-12 Kandou Labs SA Continuous time linear equalization and bandwidth adaptation using asynchronous sampling
US11563605B2 (en) 2021-04-07 2023-01-24 Kandou Labs SA Horizontal centering of sampling point using multiple vertical voltage measurements
US11374800B1 (en) 2021-04-14 2022-06-28 Kandou Labs SA Continuous time linear equalization and bandwidth adaptation using peak detector
US11496282B1 (en) 2021-06-04 2022-11-08 Kandou Labs, S.A. Horizontal centering of sampling point using vertical vernier

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPS61105933A (ja) * 1984-10-30 1986-05-24 Fujitsu Ltd サ−ビスチヤンネル信号抽出方式
JP2004208222A (ja) * 2002-12-26 2004-07-22 Fujitsu Ltd クロック復元回路およびデータ受信回路
JP2005303607A (ja) * 2004-04-09 2005-10-27 Fujitsu Ltd 等化回路を有する受信回路
JP2006222809A (ja) * 2005-02-10 2006-08-24 Fujitsu Ltd 適応等化回路

Family Cites Families (8)

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JPH0614638B2 (ja) * 1985-07-31 1994-02-23 セルヴル ミシエル 局部クロック信号と受信データ信号とを再同期させる機構
GB9102936D0 (en) * 1991-02-12 1991-03-27 Shaye Communications Ltd Digital communications systems
JP3311951B2 (ja) * 1996-12-20 2002-08-05 富士通株式会社 符号多重送信装置
US5943331A (en) * 1997-02-28 1999-08-24 Interdigital Technology Corporation Orthogonal code synchronization system and method for spread spectrum CDMA communications
US6055269A (en) * 1997-10-06 2000-04-25 Sun Microsystems, Inc. Adaptive equalization technique using twice sampled non-return to zero data
GB0504425D0 (en) 2005-03-03 2005-04-06 Texas Instruments Ltd Equalisation circuit
US7639737B2 (en) * 2006-04-27 2009-12-29 Rambus Inc. Adaptive equalization using correlation of edge samples with data patterns
US7801208B2 (en) * 2006-05-30 2010-09-21 Fujitsu Limited System and method for adjusting compensation applied to a signal using filter patterns

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61105933A (ja) * 1984-10-30 1986-05-24 Fujitsu Ltd サ−ビスチヤンネル信号抽出方式
JP2004208222A (ja) * 2002-12-26 2004-07-22 Fujitsu Ltd クロック復元回路およびデータ受信回路
JP2005303607A (ja) * 2004-04-09 2005-10-27 Fujitsu Ltd 等化回路を有する受信回路
JP2006222809A (ja) * 2005-02-10 2006-08-24 Fujitsu Ltd 適応等化回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2008105070A1 (ja) * 2007-02-27 2010-06-03 富士通株式会社 適応等化回路
JP4859977B2 (ja) * 2007-02-27 2012-01-25 富士通株式会社 適応等化回路
JP2014039292A (ja) * 2007-04-09 2014-02-27 Silicon Image Inc シリアル通信リンクのクロック・データ再生回路と使用する適応等化器
JP2012170079A (ja) * 2011-02-14 2012-09-06 Fujitsu Ltd 適応位相等化のためのシステム及び方法

Also Published As

Publication number Publication date
EP1901507A1 (en) 2008-03-19
CN101145775A (zh) 2008-03-19
JP5889272B2 (ja) 2016-03-22
US8208523B2 (en) 2012-06-26
US7920621B2 (en) 2011-04-05
US20080069276A1 (en) 2008-03-20
JP2014064328A (ja) 2014-04-10
JP2011103678A (ja) 2011-05-26
JP2011193505A (ja) 2011-09-29
US20110188564A1 (en) 2011-08-04
JP5291699B2 (ja) 2013-09-18

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