CN101145775A - 用于可编程逻辑器件的数字自适应电路和方法 - Google Patents
用于可编程逻辑器件的数字自适应电路和方法 Download PDFInfo
- Publication number
- CN101145775A CN101145775A CNA2007101540929A CN200710154092A CN101145775A CN 101145775 A CN101145775 A CN 101145775A CN A2007101540929 A CNA2007101540929 A CN A2007101540929A CN 200710154092 A CN200710154092 A CN 200710154092A CN 101145775 A CN101145775 A CN 101145775A
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- CN
- China
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
- H04L25/03885—Line equalisers; line build-out devices adaptive
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/522,284 US7920621B2 (en) | 2006-09-14 | 2006-09-14 | Digital adaptation circuitry and methods for programmable logic devices |
| US11/522,284 | 2006-09-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101145775A true CN101145775A (zh) | 2008-03-19 |
Family
ID=38814282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101540929A Pending CN101145775A (zh) | 2006-09-14 | 2007-09-14 | 用于可编程逻辑器件的数字自适应电路和方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US7920621B2 (enExample) |
| EP (1) | EP1901507A1 (enExample) |
| JP (4) | JP2008072716A (enExample) |
| CN (1) | CN101145775A (enExample) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664842A (zh) * | 2012-03-08 | 2012-09-12 | 无锡华大国奇科技有限公司 | 一种减小高速信号传输码间干扰的系统 |
| CN103546403A (zh) * | 2012-07-11 | 2014-01-29 | 联咏科技股份有限公司 | 时钟数据回复电路及方法 |
| CN112019225A (zh) * | 2020-08-27 | 2020-12-01 | 群联电子股份有限公司 | 信号接收电路、存储器存储装置及均衡器电路的校准方法 |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0504425D0 (en) * | 2005-03-03 | 2005-04-06 | Texas Instruments Ltd | Equalisation circuit |
| US8477834B2 (en) | 2006-11-16 | 2013-07-02 | Rambus, Inc. | Partial response decision-feedback equalization with adaptation based on edge samples |
| US7782088B1 (en) * | 2007-02-15 | 2010-08-24 | Altera Corporation | Sharing adaptive dispersion compensation engine among programmable logic device serial interface channels |
| JP4859977B2 (ja) * | 2007-02-27 | 2012-01-25 | 富士通株式会社 | 適応等化回路 |
| US7916780B2 (en) * | 2007-04-09 | 2011-03-29 | Synerchip Co. Ltd | Adaptive equalizer for use with clock and data recovery circuit of serial communication link |
| US8208528B1 (en) | 2007-12-13 | 2012-06-26 | Altera Corporation | Programmable adaptation convergence detection |
| US8369470B2 (en) * | 2008-11-25 | 2013-02-05 | Agere Systems, LLC | Methods and apparatus for adapting one or more equalization parameters by reducing group delay spread |
| US8484518B2 (en) * | 2009-04-28 | 2013-07-09 | Alcatel Lucent | System and method for consecutive identical digit reduction |
| US8063807B1 (en) | 2009-04-30 | 2011-11-22 | Altera Corporation | Equalization circuitry including a digital-to-analog converter having a voltage divider and a multiplexer |
| US8707244B1 (en) | 2010-08-20 | 2014-04-22 | Altera Corporation | Methods and systems for performing signal activity extraction |
| US8548108B2 (en) * | 2011-02-14 | 2013-10-01 | Fujitsu Limited | Adaptive phase equalizer |
| US8705605B1 (en) | 2011-11-03 | 2014-04-22 | Altera Corporation | Technique for providing loopback testing with single stage equalizer |
| TW201404105A (zh) * | 2012-07-06 | 2014-01-16 | Novatek Microelectronics Corp | 時脈資料回復電路及方法 |
| US11303484B1 (en) * | 2021-04-02 | 2022-04-12 | Kandou Labs SA | Continuous time linear equalization and bandwidth adaptation using asynchronous sampling |
| US11563605B2 (en) | 2021-04-07 | 2023-01-24 | Kandou Labs SA | Horizontal centering of sampling point using multiple vertical voltage measurements |
| US11374800B1 (en) | 2021-04-14 | 2022-06-28 | Kandou Labs SA | Continuous time linear equalization and bandwidth adaptation using peak detector |
| US11496282B1 (en) | 2021-06-04 | 2022-11-08 | Kandou Labs, S.A. | Horizontal centering of sampling point using vertical vernier |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61105933A (ja) | 1984-10-30 | 1986-05-24 | Fujitsu Ltd | サ−ビスチヤンネル信号抽出方式 |
| JPH0614638B2 (ja) * | 1985-07-31 | 1994-02-23 | セルヴル ミシエル | 局部クロック信号と受信データ信号とを再同期させる機構 |
| GB9102936D0 (en) * | 1991-02-12 | 1991-03-27 | Shaye Communications Ltd | Digital communications systems |
| JP3311951B2 (ja) * | 1996-12-20 | 2002-08-05 | 富士通株式会社 | 符号多重送信装置 |
| US5943331A (en) * | 1997-02-28 | 1999-08-24 | Interdigital Technology Corporation | Orthogonal code synchronization system and method for spread spectrum CDMA communications |
| US6055269A (en) * | 1997-10-06 | 2000-04-25 | Sun Microsystems, Inc. | Adaptive equalization technique using twice sampled non-return to zero data |
| JP4014501B2 (ja) | 2002-12-26 | 2007-11-28 | 富士通株式会社 | クロック復元回路およびデータ受信回路 |
| JP4331641B2 (ja) * | 2004-04-09 | 2009-09-16 | 富士通株式会社 | 等化回路を有する受信回路 |
| JP4516443B2 (ja) | 2005-02-10 | 2010-08-04 | 富士通株式会社 | 適応等化回路 |
| GB0504425D0 (en) * | 2005-03-03 | 2005-04-06 | Texas Instruments Ltd | Equalisation circuit |
| US7639737B2 (en) * | 2006-04-27 | 2009-12-29 | Rambus Inc. | Adaptive equalization using correlation of edge samples with data patterns |
| US7801208B2 (en) * | 2006-05-30 | 2010-09-21 | Fujitsu Limited | System and method for adjusting compensation applied to a signal using filter patterns |
-
2006
- 2006-09-14 US US11/522,284 patent/US7920621B2/en active Active
-
2007
- 2007-09-11 EP EP07017788A patent/EP1901507A1/en not_active Withdrawn
- 2007-09-12 JP JP2007237202A patent/JP2008072716A/ja active Pending
- 2007-09-14 CN CNA2007101540929A patent/CN101145775A/zh active Pending
-
2010
- 2010-12-27 JP JP2010291281A patent/JP5291699B2/ja not_active Expired - Fee Related
-
2011
- 2011-04-04 US US13/079,420 patent/US8208523B2/en not_active Expired - Fee Related
- 2011-04-27 JP JP2011100172A patent/JP2011193505A/ja active Pending
-
2013
- 2013-12-26 JP JP2013268773A patent/JP5889272B2/ja not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664842A (zh) * | 2012-03-08 | 2012-09-12 | 无锡华大国奇科技有限公司 | 一种减小高速信号传输码间干扰的系统 |
| CN103546403A (zh) * | 2012-07-11 | 2014-01-29 | 联咏科技股份有限公司 | 时钟数据回复电路及方法 |
| CN112019225A (zh) * | 2020-08-27 | 2020-12-01 | 群联电子股份有限公司 | 信号接收电路、存储器存储装置及均衡器电路的校准方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2011193505A (ja) | 2011-09-29 |
| JP2014064328A (ja) | 2014-04-10 |
| US7920621B2 (en) | 2011-04-05 |
| US20080069276A1 (en) | 2008-03-20 |
| JP5889272B2 (ja) | 2016-03-22 |
| US8208523B2 (en) | 2012-06-26 |
| JP2008072716A (ja) | 2008-03-27 |
| JP2011103678A (ja) | 2011-05-26 |
| JP5291699B2 (ja) | 2013-09-18 |
| US20110188564A1 (en) | 2011-08-04 |
| EP1901507A1 (en) | 2008-03-19 |
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| PB01 | Publication | ||
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| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20080319 |