JP2008022009A5 - - Google Patents

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Publication number
JP2008022009A5
JP2008022009A5 JP2007182659A JP2007182659A JP2008022009A5 JP 2008022009 A5 JP2008022009 A5 JP 2008022009A5 JP 2007182659 A JP2007182659 A JP 2007182659A JP 2007182659 A JP2007182659 A JP 2007182659A JP 2008022009 A5 JP2008022009 A5 JP 2008022009A5
Authority
JP
Japan
Prior art keywords
memory cell
line
word line
arrangement interval
ground selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007182659A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008022009A (ja
Filing date
Publication date
Priority claimed from KR1020060065040A external-priority patent/KR100777348B1/ko
Application filed filed Critical
Publication of JP2008022009A publication Critical patent/JP2008022009A/ja
Publication of JP2008022009A5 publication Critical patent/JP2008022009A5/ja
Pending legal-status Critical Current

Links

JP2007182659A 2006-07-11 2007-07-11 不揮発性メモリー素子及びその製造方法 Pending JP2008022009A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060065040A KR100777348B1 (ko) 2006-07-11 2006-07-11 비휘발성 기억 장치의 셀 어레이 구조 및 그 형성방법
US11/729,169 US8045383B2 (en) 2006-07-11 2007-03-28 Non-volatile memory devices including dummy word lines and related structures and methods

Publications (2)

Publication Number Publication Date
JP2008022009A JP2008022009A (ja) 2008-01-31
JP2008022009A5 true JP2008022009A5 (enExample) 2010-08-19

Family

ID=38830888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007182659A Pending JP2008022009A (ja) 2006-07-11 2007-07-11 不揮発性メモリー素子及びその製造方法

Country Status (2)

Country Link
JP (1) JP2008022009A (enExample)
DE (1) DE102007031278B4 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04212472A (ja) * 1990-07-13 1992-08-04 Toshiba Corp 不揮発性半導体記憶装置の製造方法
JP3808569B2 (ja) * 1996-11-14 2006-08-16 三星電子株式会社 不揮発性メモリ装置
JP4005895B2 (ja) * 2002-09-30 2007-11-14 株式会社東芝 不揮発性半導体メモリ装置
JP2004241558A (ja) * 2003-02-05 2004-08-26 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法、半導体集積回路及び不揮発性半導体記憶装置システム
DE102005058601A1 (de) * 2004-12-27 2006-07-06 Hynix Semiconductor Inc., Icheon Flash-Speicherbauelement

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