JP2007534178A5 - - Google Patents

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Publication number
JP2007534178A5
JP2007534178A5 JP2007509628A JP2007509628A JP2007534178A5 JP 2007534178 A5 JP2007534178 A5 JP 2007534178A5 JP 2007509628 A JP2007509628 A JP 2007509628A JP 2007509628 A JP2007509628 A JP 2007509628A JP 2007534178 A5 JP2007534178 A5 JP 2007534178A5
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JP
Japan
Prior art keywords
dielectric layer
conductor
forming
spacer
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007509628A
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English (en)
Japanese (ja)
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JP2007534178A (ja
JP5305651B2 (ja
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Publication date
Priority claimed from US10/709,204 external-priority patent/US20050239284A1/en
Application filed filed Critical
Publication of JP2007534178A publication Critical patent/JP2007534178A/ja
Publication of JP2007534178A5 publication Critical patent/JP2007534178A5/ja
Application granted granted Critical
Publication of JP5305651B2 publication Critical patent/JP5305651B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007509628A 2004-04-21 2005-04-21 回路の配線構造および集積回路の配線構造の製作方法 Expired - Fee Related JP5305651B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/709,204 2004-04-21
US10/709,204 US20050239284A1 (en) 2004-04-21 2004-04-21 Wiring structure for integrated circuit with reduced intralevel capacitance
PCT/US2005/013601 WO2005104212A2 (en) 2004-04-21 2005-04-21 Wiring structure for integrated circuit with reduced intralevel capacitance

Publications (3)

Publication Number Publication Date
JP2007534178A JP2007534178A (ja) 2007-11-22
JP2007534178A5 true JP2007534178A5 (enExample) 2008-05-08
JP5305651B2 JP5305651B2 (ja) 2013-10-02

Family

ID=35137032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007509628A Expired - Fee Related JP5305651B2 (ja) 2004-04-21 2005-04-21 回路の配線構造および集積回路の配線構造の製作方法

Country Status (9)

Country Link
US (2) US20050239284A1 (enExample)
EP (1) EP1743366B1 (enExample)
JP (1) JP5305651B2 (enExample)
KR (1) KR20070008599A (enExample)
CN (1) CN1943023B (enExample)
AT (1) ATE504079T1 (enExample)
DE (1) DE602005027195D1 (enExample)
TW (1) TW200539281A (enExample)
WO (1) WO2005104212A2 (enExample)

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Publication number Priority date Publication date Assignee Title
CN101471324B (zh) * 2007-12-26 2010-07-07 和舰科技(苏州)有限公司 一种超低k互连结构及其制造方法
US8497203B2 (en) 2010-08-13 2013-07-30 International Business Machines Corporation Semiconductor structures and methods of manufacture
US8492270B2 (en) 2010-09-20 2013-07-23 International Business Machines Corporation Structure for nano-scale metallization and method for fabricating same
US8957519B2 (en) 2010-10-22 2015-02-17 International Business Machines Corporation Structure and metallization process for advanced technology nodes
US8735279B2 (en) 2011-01-25 2014-05-27 International Business Machines Corporation Air-dielectric for subtractive etch line and via metallization
CN103094183B (zh) * 2011-10-29 2015-07-29 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN103117244B (zh) * 2011-11-16 2015-04-01 中芯国际集成电路制造(上海)有限公司 Ic内连线和层间介质层之间的空气间隔形成方法
CN102931127A (zh) * 2012-10-10 2013-02-13 哈尔滨工程大学 一种抗辐射加固浅槽隔离结构形成方法
US9431294B2 (en) * 2014-10-28 2016-08-30 GlobalFoundries, Inc. Methods of producing integrated circuits with an air gap
US10770539B2 (en) * 2018-09-25 2020-09-08 Nxp B.V. Fingered capacitor with low-K and ultra-low-K dielectric layers
US11094632B2 (en) * 2019-09-27 2021-08-17 Nanya Technology Corporation Semiconductor device with air gap and method for preparing the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5372969A (en) * 1991-12-31 1994-12-13 Texas Instruments Incorporated Low-RC multi-level interconnect technology for high-performance integrated circuits
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US5792706A (en) * 1996-06-05 1998-08-11 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to reduce permitivity
US5783481A (en) * 1996-06-05 1998-07-21 Advanced Micro Devices, Inc. Semiconductor interlevel dielectric having a polymide for producing air gaps
US5880026A (en) * 1996-12-23 1999-03-09 Texas Instruments Incorporated Method for air gap formation by plasma treatment of aluminum interconnects
JP2962272B2 (ja) * 1997-04-18 1999-10-12 日本電気株式会社 半導体装置の製造方法
US6242336B1 (en) * 1997-11-06 2001-06-05 Matsushita Electronics Corporation Semiconductor device having multilevel interconnection structure and method for fabricating the same
US6211561B1 (en) * 1998-11-16 2001-04-03 Conexant Systems, Inc. Interconnect structure and method employing air gaps between metal lines and between metal layers
JP4134405B2 (ja) * 1998-11-20 2008-08-20 沖電気工業株式会社 半導体素子の製造方法及び半導体素子
TW411570B (en) * 1999-02-02 2000-11-11 Nanya Technology Corp Manufacturing method of self-aligned contact
US6177329B1 (en) * 1999-04-15 2001-01-23 Kurt Pang Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets
US6342722B1 (en) * 1999-08-05 2002-01-29 International Business Machines Corporation Integrated circuit having air gaps between dielectric and conducting lines
GB0001179D0 (en) * 2000-01-19 2000-03-08 Trikon Holdings Ltd Methods & apparatus for forming a film on a substrate
TW444342B (en) * 2000-02-17 2001-07-01 United Microelectronics Corp Manufacturing method of metal interconnect having inner gap spacer
TW465039B (en) * 2000-11-06 2001-11-21 United Microelectronics Corp Void-type metal interconnect and method for making the same
US6380106B1 (en) * 2000-11-27 2002-04-30 Chartered Semiconductor Manufacturing Inc. Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures
US6936533B2 (en) * 2000-12-08 2005-08-30 Samsung Electronics, Co., Ltd. Method of fabricating semiconductor devices having low dielectric interlayer insulation layer
US6448177B1 (en) * 2001-03-27 2002-09-10 Intle Corporation Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure
KR100460771B1 (ko) * 2001-06-30 2004-12-09 주식회사 하이닉스반도체 듀얼다마신 공정에 의한 다층 배선의 형성 방법
JP2003163266A (ja) * 2001-11-28 2003-06-06 Sony Corp 半導体装置の製造方法および半導体装置
US6806534B2 (en) * 2003-01-14 2004-10-19 International Business Machines Corporation Damascene method for improved MOS transistor

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