JP2007515072A5 - - Google Patents

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Publication number
JP2007515072A5
JP2007515072A5 JP2006545545A JP2006545545A JP2007515072A5 JP 2007515072 A5 JP2007515072 A5 JP 2007515072A5 JP 2006545545 A JP2006545545 A JP 2006545545A JP 2006545545 A JP2006545545 A JP 2006545545A JP 2007515072 A5 JP2007515072 A5 JP 2007515072A5
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JP
Japan
Prior art keywords
conductive layer
forming
type region
layer
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006545545A
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English (en)
Japanese (ja)
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JP2007515072A (ja
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Priority claimed from PCT/US2004/042752 external-priority patent/WO2005059968A2/en
Publication of JP2007515072A publication Critical patent/JP2007515072A/ja
Publication of JP2007515072A5 publication Critical patent/JP2007515072A5/ja
Withdrawn legal-status Critical Current

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JP2006545545A 2003-12-17 2004-12-17 集積回路ヒューズおよびその製造方法 Withdrawn JP2007515072A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53014603P 2003-12-17 2003-12-17
PCT/US2004/042752 WO2005059968A2 (en) 2003-12-17 2004-12-17 Integrated circuit fuse and method of fabrication

Publications (2)

Publication Number Publication Date
JP2007515072A JP2007515072A (ja) 2007-06-07
JP2007515072A5 true JP2007515072A5 (enExample) 2008-02-07

Family

ID=34700102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006545545A Withdrawn JP2007515072A (ja) 2003-12-17 2004-12-17 集積回路ヒューズおよびその製造方法

Country Status (5)

Country Link
US (1) US20050133882A1 (enExample)
EP (1) EP1702361A2 (enExample)
JP (1) JP2007515072A (enExample)
CN (1) CN1894793A (enExample)
WO (1) WO2005059968A2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7146217B2 (en) * 2000-07-13 2006-12-05 Northstar Neuroscience, Inc. Methods and apparatus for effectuating a change in a neural-function of a patient
US20050258505A1 (en) * 2004-05-20 2005-11-24 Taiwan Semiconductor Manufacturing Co., Ltd. Mixed implantation on polysilicon fuse for CMOS technology
US7915093B1 (en) * 2006-10-24 2011-03-29 National Semiconductor Corporation System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process
US9917052B2 (en) * 2015-11-25 2018-03-13 International Business Machines Corporation Method of fabricating anti-fuse for silicon on insulator devices
JP6926806B2 (ja) * 2017-08-09 2021-08-25 富士電機株式会社 半導体装置及びその製造方法
JP2020155727A (ja) * 2019-03-22 2020-09-24 ソニーセミコンダクタソリューションズ株式会社 半導体装置及びこれを備えた電子機器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5015604A (en) * 1989-08-18 1991-05-14 North American Philips Corp., Signetics Division Fabrication method using oxidation to control size of fusible link
US5384727A (en) * 1993-11-08 1995-01-24 Advanced Micro Devices, Inc. Fuse trimming in plastic package devices
US5622892A (en) * 1994-06-10 1997-04-22 International Business Machines Corporation Method of making a self cooling electrically programmable fuse
US6033939A (en) * 1998-04-21 2000-03-07 International Business Machines Corporation Method for providing electrically fusible links in copper interconnection
US5973977A (en) * 1998-07-06 1999-10-26 Pmc-Sierra Ltd. Poly fuses in CMOS integrated circuits
US6031275A (en) * 1998-12-15 2000-02-29 National Semiconductor Corporation Antifuse with a silicide layer overlying a diffusion region
US6323534B1 (en) * 1999-04-16 2001-11-27 Micron Technology, Inc. Fuse for use in a semiconductor device
JP3445536B2 (ja) * 1999-10-04 2003-09-08 三洋電機株式会社 半導体装置
US6624499B2 (en) * 2002-02-28 2003-09-23 Infineon Technologies Ag System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient
US6815800B2 (en) * 2002-12-09 2004-11-09 Micrel, Inc. Bipolar junction transistor with reduced parasitic bipolar conduction
US6911360B2 (en) * 2003-04-29 2005-06-28 Freescale Semiconductor, Inc. Fuse and method for forming
US6933591B1 (en) * 2003-10-16 2005-08-23 Altera Corporation Electrically-programmable integrated circuit fuses and sensing circuits
JP4004484B2 (ja) * 2004-03-31 2007-11-07 シャープ株式会社 固体撮像素子の製造方法

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