JP2007273628A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2007273628A JP2007273628A JP2006095798A JP2006095798A JP2007273628A JP 2007273628 A JP2007273628 A JP 2007273628A JP 2006095798 A JP2006095798 A JP 2006095798A JP 2006095798 A JP2006095798 A JP 2006095798A JP 2007273628 A JP2007273628 A JP 2007273628A
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Abstract
【解決手段】本発明の半導体装置の製造方法は、互いに対応する電極同士(例えば、電極15及び電極41同士)で接合される一対の基体10A及び40のうち、少なくとも一方の基体10A上に磁性バンプ34を形成するバンプ形成工程と、前記一方の基体10A上に形成された前記磁性バンプ34の磁力により、前記一方の基体10Aにおける電極15の位置を、該電極15に対応した他方の基体40における電極41との接合位置に合わせる位置決め工程と、前記一方の基体10Aにおける前記電極15と、前記他方の基体40における前記電極41とを接合する電極接合工程とを少なくとも含み、前記位置決め工程が、前記一方の基体10Aの複数個に対して一括して行われる。
【選択図】図2K
Description
この為、半導体素子(半導体チップ)をその支持基板に実装する方法として、当該半導体チップの主面を支持基板に対向させ、当該半導体チップの電極を支持基板上の電極に接続する所謂フリップチップ(フェイスダウン)実装が採用されている。
フリップチップ実装に於いては、半導体チップの電極パッド上に外部接続用突起電極が形成され、当該突起電極が支持基板上の電極配線と機械的・電気的に接続される。
図7Aに示されるように、当該BGA型半導体装置にあっては、支持基板(インターポーザー、回路基板とも称される)7の表面上に、半導体チップ1Aがフリップチップ実装されており、当該半導体チップ1Aにおける電極パッド上のバンプ1Bと支持基板7における電極7Bとが機械的・電気的に接続された状態にて、モールド樹脂8により封止されている。
そして、支持基板7の裏面(他方の主面)には、外部接続端子としての半田ボール9が配設されている。
次いで、ダイシングブレードBを用いるブレードダイシングなどの方法により、半導体基板1を半導体チップ1Aに個片化した後、図7Dに示すように、ダイシングテープ3を拡張して半導体チップ1A相互の間隔を大きくする。
その後、突上げ用ピン(図示せず)を用いて、ダイシングテープ3の下側から半導体チップを突き上げることにより、当該半導体チップ1Aをダイシングテープ3から剥離すると共に、当該半導体チップ1Aの上方に待機させた吸着ツールT1を用いて半導体チップ1Aをピックアップし、当該半導体チップ1Aをチップトレー4に移送して収納する。
次に、図7Eに示すように、吸着ツールT2を用いて、半導体チップ1Aをチップトレー4からピックアップする。このとき、吸着位置を正確に合わせるために、チップトレー4内の半導体チップ1Aを、半導体チップ1Aの上方に配置したカメラ5により認識し、位置補正を行ってからピックアップする。
その後、半導体チップ1Aを吸着・保持した吸着ツールT2を上下反転させ、上方に待機させた他の吸着ツールT3に半導体チップ1Aを受け渡す。
次いで、図7Fに示すように、当該吸着ツールT3に保持された半導体チップ1Aに於けるパッドの位置を下方に配置された下カメラ6Aによって認識する一方、当該半導体チップ1Aが搭載される支持基板7に於ける電極の位置を、上方に配置された上カメラ6Bで認識し、これらのカメラ6A及び6Bの認識結果から、電極同士を正確な位置に対応させるために、吸着ツールT3のX・Y・θ位置を補正する。
そして、図7Gに示すように、ペースト状又はフィルム状のアンダーフィル材7Aが予め塗布された支持基板7上に、複数個の半導体チップ1Aを順次搭載する。
次いで、図7Hに示すように、支持基板7の半導体チップ1A搭載面をモールド樹脂8により一括してモールド処理する。
次いで当該支持基板7の裏面に、外部接続用端子となる半田ボール9を配設する。
しかる後、図7Iに示すように、第二のダイシングブレードBを用いたブレードダイシングにより、モールド樹脂8及び支持基板7を切断し、前記図7Aに示す個片化された半導体装置を得る。
例えば、特許文献1には、スルーホールの内部に充填した磁性体により位置合わせを行う方法が開示され、また特許文献2には、チップに磁石を配設し、基板上に配設された磁性体と相互に引き合うことによりチップを基板上に実装する方法が開示されている。
一方、特許文献3には、プリント配線板上に形成された磁性体からなる突起部を有する電極と、基材上に形成された磁性層を有する電極とを、磁力により位置合わせして接続する方法が、更に特許文献4には、ICチップの磁性体片と回路基板の磁性体層とを磁力により位置合わせすることにより、電極同士を接続する方法が記載されている。
しかしながら、これらの方法においては、磁力によって簡易に電極同士の位置合わせを行うことができるものの、その処理はいずれもチップ単位で行うため生産性が悪い。
本発明は、一対の基体(例えば、半導体チップと支持基板(回路基板)、或いは半導体チップと半導体チップ等)における電極同士を短時間に接続し、低コストで効率的に半導体装置を得ることができる半導体装置の製造方法を提供することを目的とする。
本発明の半導体装置の製造方法は、互いに対応する電極同士で接合される一対の基体のうち、少なくとも一方の基体上に磁性バンプを形成するバンプ形成工程と、前記一方の基体上に形成された前記磁性バンプの磁力により、前記一方の基体における電極の位置を、該電極に対応した他方の基体における電極との接合位置に合わせる位置決め工程と、前記一方の基体における前記電極と、前記他方の基体における前記電極とを接合する電極接合工程とを少なくとも含み、前記位置決め工程が、前記一方の基体の複数個に対して一括して行われることを特徴とする。
該半導体装置の製造方法では、前記バンプ形成工程において、互いに対応する電極同士で接合される前記一対の基体のうち、少なくとも前記一方の基体上に前記磁性バンプが形成される。前記位置決め工程において、前記一方の基体上に形成された前記磁性バンプの磁力により、前記一方の基体における前記電極の位置が、該電極に対応した前記他方の基体における前記電極との接合位置に合わせられる。このとき、前記位置決め工程が、前記一方の基体の複数個に対して一括して行われる。前記電極接合工程において、前記一方の基体における前記電極と、前記他方の基体における前記電極とが接合される。
その結果、前記一対の基体における電極同士が容易かつ短時間で接合され、低コストで効率的に半導体装置が製造される。
本発明による半導体装置の製造方法の第1の実施例を、図面を用いて説明する。
本実施例にあっては、図2Aに示す半導体基板10に形成された複数個の半導体チップ10Aそれぞれの表面に、磁性バンプを形成する。一方、図2Fに示す支持基板40上にも、各半導体チップ10Aに於ける磁性バンプと対応する磁性バンプを形成する。
なお、ここでは、半導体チップ10Aを前記一方の基体と称し、支持基板40を前記他方の基体と称する。これらの基体に形成された電極を相互に接続することにより、一対の基体としての半導体装置を製造する。
なお、図1A〜図1Jは、一枚の半導体基板(半導体ウェーハ)10に形成された複数個の半導体チップのうち、一つの半導体チップを特徴的に示すものであり、それぞれに於いて、右側の図は当該半導体チップの平面図を示し、左側の図は当該平面図に於けるA−A’断面を示す。
当該金属層13の材料は、アルミニウム(Al)、銅(Cu)、金(Au)、銀(Ag)、ニッケル(Ni)或いはタングステン(W)等、及びこれらの合金が挙げられ、目的に応じて適宜選択される。
そして、当該感光性樹脂層31を現像し、図1Cに示すように、感光性樹脂層31に、所定の金属層13を露出する開口31Aを形成する。本例では、半導体チップ10A上の2箇所に、それぞれ隣接する2つの金属層13上に跨がる開口31Aを形成する。
当該第1のメタルマスク33には、前記感光性樹脂層31に於いて開口31Aが形成されていない部位に対応して開口33A及び33Bが形成されている。当該開口33A及び33Bは半導体チップ10Aのほぼ対角に位置し、且つ互いに異なる形状を有する。
尚、図1Eにあっては、第1のメタルマスク33の外形、並びに開口33A及び33Bを、その平面形状を示す右側の図に於いて、破線で示している。
当該磁性体ペースト34は、磁石に引き寄せられる微粒子を、接着性を有する樹脂に練入してペースト状にしたものであり、当該微粒子は、目的に応じて適宜選択することができるが、例えば、磁化を消失するキュリー点(Tc)が、樹脂を半硬化させるためのキュアー温度以下、例えば、100℃以下であるのが好ましい。
このような微粒子としては、例えば、ニッケル(Ni)−亜鉛(Zn)系のソフトフェライト(「XS1」;FDK株式会社製)を使用することができる。
ここで、磁性体パターン34Aは、開口33A内に充填された磁性体ペースト34から形成されたものであり、磁性体パターン34Bは、開口33B内に充填された磁性体ペースト34から形成されたものである。なお、磁性体パターン34A及び34Bは、半硬化のための熱処理により磁化を消失する。
当該第2のメタルマスク36には、感光性樹脂層31に於ける二つの開口31Aに相当する部位に当該開口31Aよりも大なる開口36Aが配設され、一方、磁性パターン34A及び34Bの形成領域には、前記磁性体パターン34A及び34Bよりも大なる開口36B及び36Cが形成されている。
このとき、開口36A内に前記金属層14が表出され、また開口36B及び36C内に磁性体パターン34A及び34Bがそれぞれ表出されるように、当該第2のメタルマスク36を位置合わせする。
尚、図1Hにあっても、第2のメタルマスク36の外形並びに開口36Aを、その平面形状を示す右側の図に於いて、破線で示している。
しかる後、当該Agペースト37を、80〜110℃程度の温度下で半硬化(所謂Bステージキュアー)させ、感光性樹脂層31の開口31A内の金属パッド14と電気的に接続されてなる電極15を形成する。
なお、前記磁性体ペースト34と銀(Ag)ペースト37の半硬化温度が互いに近い場合、銀(Ag)ペースト37の半硬化処理と磁性体ペースト34の半硬化処理とを同時に行ってもよい。
当該接着性を有する絶縁材料としては、常温では固体であり接着性を示さず、例えば、約110℃以上の温度で軟化し、これよりも高温の温度、例えば約130℃以上で硬化する性質を有するものであり、該一端硬化した後は常温でも硬化した状態を保つ必要がある。
当該絶縁材料としては、エポキシ樹脂系のフィルム状接着剤、及びBステージ接着剤を用いることができ、目的に応じて適宜選択される。
当該絶縁材料を用いることにより、後の工程に於ける支持基板と半導体チップとの間にアンダーフィル材を充填する工程を省略することができ、製造工程の簡略化を図ることができる。
この結果、電極15、磁性体パターン34A及び34B、並びに絶縁膜16はその高さがほぼ均一となり連続する平面を形成する。この様な表面形態により、後のボンディング時の荷重或いは加熱温度等の条件が緩和される。
即ち、被処理半導体基板11の温度を、電極15、磁性体パターン34A及び34B、並びに絶縁膜16の軟化(半硬化)温度のうちの低値である約80℃よりもより低温(例えば、50℃)に設定・保持する。そしてバイトを用いた切削加工により上昇する電極15及び絶縁膜16の温度を、80℃よりも低温に制御しつつ、切削加工工程の全体を通して80℃よりも低い温度範囲を保持しながら平坦化処理する。
このような平坦化処理により、半導体チップ10A上には、絶縁膜16に囲まれた電極15、磁性体パターン34A及び34B(以下、「磁性バンプ34」と総称することがある)の被切削面が表出する。
尚、絶縁膜16が不透明であると、平坦化された半導体チップ10Aの表面から絶縁膜16の内部を覗うことができず、ROM内容の書き換え等の記憶情報の不正な改ざん等を防止することができる。
かかるタイシング処理及びダイシング処理により個片化された半導体チップを、支持基板に接続・搭載する工程を図2A乃至図2Oをもって示す。
尚、図2A〜図2Oに示す工程に於いては、電極15及び磁性バンプ34などの形成位置が、前記図1A〜図1Jに示す態様とは異なる。
そして、ダイシングブレード(図示せず)によりダイシング処理し、図2Bに示されるように半導体基板10を個々の半導体チップ10Aに分割・個片化する。当該個片化処理は、ブレード法に代えて、レーザーを用いた光加工或いはエッチング等の化学処理などにより行ってもよい。
尚、図2Bは、ダイシングテープ51上の半導体基板10の垂直断面を示し、破線で囲まれた領域Xに於ける、個片化された半導体チップ10Aを図2Cに示す。
また、個々の半導体チップ10Aが搭載される領域には、当該半導体チップ10Aに於ける磁性体パターン34A及び34B(磁性バンプ34)に対応して、磁性体パターン44A及び44B(以下、「磁性バンプ44」と総称することがある)が配設される。
即ち、当該支持基板40上の磁性体パターン44A及び44Bは、半導体チップ10A上の磁性体パターン33A及び33Bと対向し互いに吸着する際に、半導体チップ10A上の電極15と、支持基板40上の電極41とが接続されるように選択的に配置されている。
当該磁性体パターン44A及び44Bを形成する磁性体としては、後の工程に於いて電極15の樹脂及び絶縁膜16の樹脂を硬化するための熱処理の際の温度よりも低い、例えば150℃のキュリー点(Tc)を有する磁性体を適用するのが好ましい。このような磁性体としては、例えば、バナジウム(Ba)系のハードフェライト(「XH1」;FDK株式会社製)が挙げられる。
尚、半導体チップ10Aを搭載・接続する前の支持基板40に於いては、磁性体パターン44A及び44Bは磁化を有している。
以上が、本発明の前記半導体装置の製造方法における前記バンプ形成工程に相当する。
尚、半導体チップ10Aの相互の間隔を、支持基板40上の半導体チップ搭載部のレイアウトに対応する寸法にまで拡げるのが望ましい。
尚、図2Hに示すように、基板保持台45には加熱用ヒーター46が埋設されており、支持基板40を必要に応じて加熱することができる。
当該WFテーブル53の下には、多数の突上げ用ピン54が配設されており、当該突上げ用ピン54は、WFテーブル53に設けられた孔53Aを通して上方向即ち半導体チップ10A側に移動し突出可能とされている。
尚、WFテーブル53表面には、吸着装置(図示せず)に接続された複数個の真空吸引孔53Bが配設されており、ダイシングテープ51は当該真空吸引孔53Bを通しては吸引され、WFテーブル53上に固定される。
図2Jに示すように、複数の半導体チップ10Aの上方に、前記支持基板40を配置した状態にて、前記突上げピン54を上昇させる。これにより半導体チップ10Aは、ダイシングテープ51から剥離される。
ここで、突上げピン54の上昇量は、磁性バンプ34と磁性バンプ44との間に働く磁力、或いは半導体チップ10Aのサイズなどに応じて適宜選択され、半導体チップ10Aをダイシングテープ51から剥離することができれば足りる。従って当該突上げピン54がダイシングテープ51を突き破る必要は無い。
その結果、半導体チップ10Aは、支持基板40に対応した適切な位置に自己整列される。
突上げピン54は半導体基板10の全面を網羅する範囲に配設されており、かかる剥離処理を半導体基板10に形成された複数個の半導体チップ10Aについて同時に行うため、全ての半導体チップ10Aは支持基板40に位置合わせが略同時になされる。
以上が、本発明の前記半導体装置の製造方法に於ける前記位置決め工程に相当する。
尚、かかる工程に於いて、図2I或いは図2Kに示される如く、支持基板40に微小な振動を加えることにより、その効果を向上せしめることができる。
しかる後、支持基板40の表裏を反転させ、当該支持基板40の半導体チップ10Aの被搭載面を上とする。
当該加圧ツール55を下降させ、図2Mに示すように半導体チップ10Aに接触させた後、一定時間加圧すると共に加熱する。
この結果、半導体チップ10Aと支持基板40とは、それぞれ対向する位置関係で位置決めされた状態にて、電極間(電極15及び電極41間)で接続される。
以上が、本発明の前記半導体装置の製造方法における前記電極接続工程に相当する。
しかる後、支持基板40の裏面に外部接続端子となる半田ボール58を形成する。これらは総て前記半導体ウェーハ単位で一括して処理する。
しかる後、図2Oに示すように、当該支持基板40を、WFリング50に貼られたダイシングテープ51上に貼り付ける。
そして、ダイシングブレード59によるダイシングにより、半導体チップ10Aの間の封止樹脂部及び支持基板40をダイシングし、図3Aに示す個片化された半導体装置100を形成する。当該半導体装置100は、BGA型半導体装置と称される。
従って、製造に要する時間を大幅に短縮することができ、製造コストの低減を実現することができる。
本発明の半導体装置の製造方法を用いて製造した、2段スタック型マルチチップ構造を有する半導体装置の一例を図3Bに示す。
同図に示す、2段スタック型マルチチップ構造半導体装置200に於いては、支持基板40の一方の主面(上面)上に2個の半導体チップ10A及び10Bが積層されて搭載されている。
下段(1段目)の半導体チップ10Aは、当該半導体チップ10A表面に形成された磁性バンプ34(34A及び34B)と、支持基板40に形成された磁性バンプ44(44A及び44B)との間に働く磁力により、当該支持基板40に引き寄せられて位置合わせされ、半導体チップ10A表面に形成された電極15と、支持基板40に於ける電極41とが接続された状態、即ち半導体チップ10Aがフリップチップ(フェイスダウン)接続された状態とされて、アンダーフィル材16により固着されている。
また、上段(2段目)の半導体チップ10Bは、電子回路、配線パターンなどが形成されている面を上面にして、1段目(下段)の半導体チップ10Aにて搭載され、ダイアタッチ17にて固着されている。
支持基板40の他方の主面(下面)には、外部接続用端子として半田ボール58が配設されており、当該半田ボール58は電極41に固着されている。
そして、前記半導体チップ10Bの電極にワイヤWの一端が結合され、該ワイヤWの他端は支持基板40に於ける電極41を介して外部接続用端子に接続されて、支持基板40、半導体チップ10A及び半導体チップ10Bが相互に電気的に接続され、かかる状態にて封止樹脂57により封止されている。
同図に示す2段スタック型マルチチップ構造半導体装置300に於いては、支持基板40の一方の主面(上面)上に、2個の半導体チップ10C及び10Aが互いの電子回路・配線パターンなどが形成されている面を対向させて搭載されている。
即ち、下段(1段目)の半導体チップ10Cは、配線パターンが形成されている面を上面にして、支持基板40上にダイアタッチ17を用いて固着されている。
また、上段(2段目)の半導体チップ10Aは、半導体チップ10Aに形成された磁性バンプ34(34A及び34B)と、半導体チップ10Cに形成された磁性バンプ44(44A及び44B)との間に働く磁力により、当該半導体チップ10Cに引き寄せられて位置合わせされ、半導体チップ10Aに於ける電極15と、半導体チップ10Cにおける電極41とが接続された状態、即ち半導体チップ10Cに対しフリップチップ(フェイスダウン)接続された状態とされて、アンダーフィル材16により固着されている。
また、支持基板40の他方の主面(下面)には、外部接続用端子として半田ボール58が配設されている。
そして、半導体チップ10Cの電極にワイヤWの一端が結合され、当該ワイヤWの他端は支持基板40に於ける電極(図示せず)を介して外部接続用端子に接続され、支持基板40、半導体チップ10A及び半導体チップ10Bが相互に電気的に接続され、かかる状態にて封止樹脂57により封止されている。
同図に示す2段スタック型マルチチップ構造を有する半導体装置400に於いては、支持基板40の一方の主面(上面)上に、外形寸法の異なる2個の半導体チップ10A及び10Dが、互いの電子回路・配線パターンなどが形成されている面を対向させずに重ねられ、当該支持基板40の一方の主面に対しそれぞれがフリップチップ(フェイスダウン)接続された状態とされている。
下段(1段目)の半導体チップ10Aは、当該半導体チップ10Aに形成された磁性バンプ34a及び34bと、支持基板40上に形成された磁性バンプ44a及び44bとの間に働く磁力により、支持基板40に引き寄せられて位置合わせされ、当該半導体チップ10Aにおける電極15と、支持基板40における電極41とが接続された状態にて、アンダーフィル材16により固着されている。
また、上段(2段目)の半導体チップ10Dは、下段(1段目)の半導体チップ10Aよりも外形寸法が大きく、当該半導体チップ10Dに形成された磁性バンプ34A及び34Bと、支持基板40に形成された磁性バンプ44A及び44Bとの間に働く磁力により、支持基板40に引き寄せられて位置合わせされ、当該半導体チップ10Dに於ける電極15と、支持基板40に於ける電極41とが接続されている。
更に、支持基板40の他方の主面(下面)には、外部接続用端子として半田ボール58が配設されている。
そして、支持基板40、半導体チップ10A及び半導体チップ10Dが電気的に接続された状態にて、封止樹脂57により封止されている。
尚、磁性バンプの大きさは、半導体チップの形状、配置される位置に応じて適宜選択される。
本発明の半導体装置の製造方法の第2の実施例を、以下に図面を用いて説明する。
本実施例にあっては、半導体チップが前記一方の基体に相当し、短冊状基板が前記他方の基体に相当する。
また、前記位置決め工程が、前記半導体チップ上に形成された磁性バンプと、トレー板上に形成された磁性バンプとの間に働く磁力により行われ、その後、前記半導体チップと前記短冊状基板とを接続することにより、前記一対の基体としての半導体装置(パッケージ)を製造することができる。
また、本実施例2にあっては、前記電極接続工程が、実施例1のような半導体基板単位の一括処理ではなく、半導体チップが複数個列状に配置されたチップ列を対象として、その複数列を単位として一括処理を行う。
一方、トレー板60上にも、前記半導体チップ10A上に形成された磁性バンプに対応する磁性バンプを形成する(図4F参照)。
当該磁性バンプの形成は、前記実施例1にて適用した方法と同様な方法により実施することができる。
尚、ダイシングテープ51上に於いてダイシング処理された半導体基板10の垂直断面図を図4Bに示し、図4B中、破線で囲まれたX部分に於ける個片化された半導体チップ10Aの拡大図を図4Cに示す。
図4Cに於いて、半導体チップ10Aの半導体基板11上には、電極15、絶縁膜16、磁性バンプ34A及び34Bが配設されている。
前記磁性体パターン64A及び64Bの材料は、目的に応じて適宜選択することができ、実施例1において支持基板40上に形成した、磁性体パターン44A及び44Bと同様なものを使用することができる。
以上が、本発明の前記半導体装置の製造方法に於ける前記バンプ形成工程に相当する。
そして、当該半導体基板10上には、チップ剥離部Yをセットする。
当該チップ剥離部Yは、図4Jに示すように、WFテーブル53及び突上げピン54を具備している。
そして、図4Lに示すように、当該チップ剥離部Yに於ける突上げピン54を下方に押し下げ、図4Kに示すように、半導体チップ10Aをダイシングテープ51から剥離して、トレー板60の一方の主面上に吸着せしめる。
図4Lに於いて、破線で囲まれたX部分における、個片化された半導体チップ10Aの拡大図を図4Mに示す。
図4Mに示すように、半導体チップ10Aの真下には、トレー板60に形成された、磁性体パターン64A及び64B(磁性バンプ64)が配置されており、磁性バンプ34と磁性バンプ64との間に働く磁力により、半導体チップ10Aにおける磁性バンプ34とトレー板60における磁性バンプ64とが互いに引き寄せられ合う。その結果、半導体チップ10Aが、トレー板60上の適度な位置に自己整列される。ここで、トレー板60に微小な振動を加えると、よりその効果が向上する。
以上が、本発明の前記半導体装置の製造方法に於ける前記位置決め工程に相当する。
即ち、図4N及び図4Oに示すように、トレー板60上に自己整列して保持された複数個の半導体チップ10Aのうち、列状に並ぶ複数個の半導体チップを同時に、接続ツール66により吸着する。
ここで、当該接続ツール66は、複数個の吸着ヘッドを具備し、各吸着ヘッドは独立しており、そのヘッド間隔も伸縮させることが可能とされている。従って、トレー板60上に保持された複数個の半導体チップ10Aを吸着する際には、当該半導体チップの搭載された間隔に対応させることができる。
この様な接続ツール66を用い、トレー板60上に保持された複数個の半導体チップ10Aを真空吸着する。
トレー板60上に保持された半導体チップ10Aは、前述の如く、当該半導体チップ10Aに形成された磁性バンプ34と、トレー板60上に形成された磁性バンプ64との間に働く磁力により保持されているが、接続ツール66には該磁力を上回る吸着力を発揮させることにより、半導体チップ10Aは容易にピックアップされる。
尚、接続ツール66には、図4Oに示すように、ヒーター67が埋設されており、必要に応じて半導体チップ10Aを加熱することができる。
上述の如く、トレー板60と半導体チップ10Aとの位置合わせは既に行われており、接続ツール66の移動精度は保たれているので、半導体チップ10Aと短冊状基板65との位置合わせに、認識等の特別な処理は必要とされない。
その結果、半導体チップ10Aと短冊状基板65とは、それぞれ対向する位置関係で位置決めされた状態にて、電極間(電極15及び電極41)で本接続される。これらは総て半導体チップ10Aが複数個列状に配置されたチップ列の複数列単位で一括処理する。
以上が、本発明の前記半導体装置の製造方法における電極接続工程に相当する。
そして、図4Sに示すように、短冊状基板65を、WFリング50に貼られたダイシングテープ51に貼り付ける。
しかる後、ブレード59によるパッケージダイシングによって、樹脂部と短冊状基板65を個片化することにより、図3Aに示す半導体装置100が形成される。
また、前記実施例1にあっては支持基板として円形状基板を用いたのに対し、実施例2では短冊状基板を用いている。本発明の前記半導体装置の製造方法によれば、支持基板の形状に合わせて電極間を効率よく接続することができる。
本発明の半導体装置の製造方法の第3の実施例を、以下に図面を用いて説明する。
本実施例3では、半導体チップが前記一方の基体に相当し、帯状基板が前記他方の基体に相当する。
また、前記位置決め工程が、前記半導体チップ上に形成された磁性バンプと、前記帯状基板上に形成された磁性バンプとの間に働く磁力により行われ、その後、前記電極接続工程により、互いに対応する前記半導体チップに於ける電極と、前記帯状基板に於ける電極とを接続した状態にて、前記半導体チップを前記帯状基板と共に、リールに巻き取って収納する。
また、本実施例3にあっては、電極接続工程が、前記半導体チップが複数個列状に配置されたチップ列の一列毎に、一括して処理される。
ここで、前記磁性バンプの形成は、図1A〜図1Jに示す、実施例1と同様な方法により行うことができる。
また、帯状基板70の一方の表面には、半導体チップ10A上に形成された磁性体パターン34A及び34B(磁性バンプ34)に対して鏡像をなすように、磁性体パターン74A及び74B(以下、「磁性バンプ74」と総称することがある)を形成する(図5F参照)。
以上が、本発明の前記半導体装置の製造方法における前記バンプ形成工程に相当する。
そして、図示しないブレードによりダイシングし、半導体基板10から、半導体チップ10Aに個片化する。
該個片化後、ダイシングテープ51を拡張し、図5Cに示すように、半導体チップ10Aの相互の間隔を拡大する。
その後、図5Dに示すように、先に準備しておいた帯状基板70を、半導体チップ10Aの上方に配置する。ここでは、正確な位置合わせは必要とせず、大体の位置が合っていればよい。
ここで、図5Fに示すように、半導体チップ10Aの下方には、2〜5程度の複数チップ分の突上げピン54が配置されている。該突上げピン54は、上方向に移動可能に設けられており、このため、WFテーブル53には、突上げピン54の逃げ穴が設けられている。また、WFテーブル53には、真空吸着孔53Aが設けられており、図示しないバキューム源により吸引され、ダイシングテープ51は、WFテーブル53上に吸着固定される。
この状態にて、突上げピン54を上昇させることにより、半導体チップ10Aがダイシングテープ51から剥離される。
これらの処理は、2〜5程度の複数チップ単位で行われるが、突上げピン54の位置を固定し、これに合わせて剥離する半導体チップ10Aが、突上げピン54の位置の上方に配置されるように、半導体チップ10Aの位置を動かす。
以上が、本発明の前記半導体装置の製造方法における前記位置決め工程に相当する。
その後、半導体チップ10Aが接続された帯状基板70は、リール71に巻回される。このとき、半導体チップ10Aの背面とリール71とが、直接接触しないように挿間紙Sを挿入する。
以上が、本発明の前記半導体装置の製造方法に於ける前記電極接続工程に相当する。
また、実施例3では、帯状の支持基板を用いて処理するので、厚さの薄い、例えばFPC(フレキシブルプリント回路)基板を用いた半導体装置の製造に好適である。
その応用例として、図6A及び図6Bに、イメージセンサモジュールの一例を示す。なお、図6Aは、イメージセンサモジュールの上面図を示し、図6Bは、図6A中、破線で囲まれたX部分におけるセンサチップ部の垂直断面拡大図を示す。実施例3の半導体装置の製造方法を用い、前記帯状基板70としてのFPC基板と、前記半導体チップ10Aとしての、受光部10aを有するイメージセンサチップとを、これらの電極(電極75及び電極15)間で接続し、更に必要に応じて、受動部品を搭載すると、図6A及び図6Bに示す、前記半導体装置としてのセンサモジュール500が完成する。
当該センサモジュール500は、携帯電話等の最終製品の実装基板に実装される。
もちろん、帯状基板を短冊状に分離し、その後、封止樹脂によりモールド処理し、更に半田ボールを配設して、更にダイシングにより個片化することにより、前記BGA型半導体装置を形成することもできる。
例えば、フリップチップボンディングでは、現状、一つの半導体チップ当たり30〜60秒間所要する処理が、本発明の半導体装置の製造方法を用いると、チップサイズが6mm□の場合、700個程度の半導体チップを一括してピックアップし、それぞれの電極に移動してサイクル20秒で処理することも可能となり、0.028秒/チップの速度を実現することができる。
(付記1) 互いに対応する電極同士で接合される一対の基体のうち、少なくとも一方の基体上に磁性バンプを形成するバンプ形成工程と、
前記一方の基体上に形成された前記磁性バンプの磁力により、前記一方の基体における電極の位置を、該電極に対応した他方の基体における電極との接合位置に合わせる位置決め工程と、
前記一方の基体における前記電極と、前記他方の基体における前記電極とを接合する電極接合工程とを少なくとも含み、
前記位置決め工程が、前記一方の基体の複数個に対して一括して行われることを特徴とする半導体装置の製造方法。
(付記2) 一方の基体上に形成された磁性バンプの磁力が、磁化を有する磁性バンプにより発現される付記1に記載の半導体装置の製造方法。
(付記3) 一方の基体が半導体チップであり、他方の基体が半導体チップ及び回路基板のいずれかである付記1から2のいずれかに記載の半導体装置の製造方法。
(付記4) 位置決め工程が、一方の基体上に形成された磁性バンプと、他方の基体上に形成された磁性バンプとの間に働く磁力により行われる付記1から3のいずれかに記載の半導体装置の製造方法。
(付記5) 位置決め工程が、一方の基体上に形成された磁性バンプと、トレー板上に形成された磁性バンプとの間に働く磁力により行われる付記1から3のいずれかに記載の半導体装置の製造方法。
(付記6) 一方の基体の複数個が、トレー板上に配列されることを含む付記5に記載の半導体装置の製造方法。
(付記7) 一方の基体が配列された基体列の数が複数である付記6に記載の半導体装置の製造方法。
(付記8) 電極接合工程が、一方の基体からなる基体列の複数に対して同時に行われる付記7に記載の半導体装置の製造方法。
(付記9) 他方の基体が、短冊状基板である付記8に記載の半導体装置の製造方法。
(付記10) 電極接合工程が、一方の基体が複数個配列された基体列の一列毎に行われる付記1から7のいずれかに記載の半導体装置の製造方法。
(付記11) 他方の基体が、帯状基板である付記10に記載の半導体装置の製造方法。
(付記12) 電極接合工程が、互いに対応する電極同士を接合した状態にて、一方の基体を他方の基体と共にリールに巻き取ることを含む付記11に記載の半導体装置の製造方法。
10A 半導体チップ
15 電極
16 絶縁膜(アンダーフィル)
34 磁性バンプ(磁性体パターン34A及び34B)
40 支持基板
41 電極
44 磁性バンプ(磁性体パターン44A及び44B)
45 基板保持台
46,56 ヒーター
50 WFリング
51 ダイシングテープ
53 ウェーハテーブル
54 突上げピン
55 加圧ツール
57 封止樹脂
58 ボール
59 ブレード
60 トレー板
64 磁性バンプ(磁性体パターン64A及び64B)
65 短冊状基板
66 吸着ツール
67 ヒーター
70 帯状基板
71 リール
72,73 ヒーターブロック
74 磁性バンプ(磁性体パターン74A及び74B)
75 電極
76 加圧ツール
100 パッケージ(半導体装置)
S 挿間紙
W ワイヤ
Claims (10)
- 互いに対応する電極同士で接合される一対の基体のうち、少なくとも一方の基体上に磁性バンプを形成するバンプ形成工程と、
前記一方の基体上に形成された前記磁性バンプの磁力により、前記一方の基体における電極の位置を、該電極に対応した他方の基体における電極との接合位置に合わせる位置決め工程と、
前記一方の基体における前記電極と、前記他方の基体における前記電極とを接合する電極接合工程とを少なくとも含み、
前記位置決め工程が、前記一方の基体の複数個に対して一括して行われることを特徴とする半導体装置の製造方法。 - 一方の基体が半導体チップであり、他方の基体が半導体チップ及び回路基板のいずれかである請求項1に記載の半導体装置の製造方法。
- 位置決め工程が、一方の基体上に形成された磁性バンプと、他方の基体上に形成された磁性バンプとの間に働く磁力により行われる請求項1から2のいずれかに記載の半導体装置の製造方法。
- 位置決め工程が、一方の基体上に形成された磁性バンプと、トレー板上に形成された磁性バンプとの間に働く磁力により行われる請求項1から2のいずれかに記載の半導体装置の製造方法。
- 一方の基体の複数個が、トレー板上に配列されることを含む請求項4に記載の半導体装置の製造方法。
- 一方の基体が配列された基体列の数が複数である請求項5に記載の半導体装置の製造方法。
- 電極接合工程が、一方の基体からなる基体列の複数に対して同時に行われる請求項6に記載の半導体装置の製造方法。
- 他方の基体が、短冊状基板である請求項7に記載の半導体装置の製造方法。
- 電極接合工程が、一方の基体が複数個配列された基体列の一列毎に行われる請求項1から6のいずれかに記載の半導体装置の製造方法。
- 電極接合工程が、互いに対応する電極同士を接合した状態にて、一方の基体を他方の基体と共にリールに巻き取ることを含む請求項9に記載の半導体装置の製造方法。
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FR3066317B1 (fr) * | 2017-05-09 | 2020-02-28 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de fabrication d'un dispositif d'affichage emissif a led |
CN111276506B (zh) * | 2018-12-05 | 2023-09-12 | 錼创显示科技股份有限公司 | 载板结构及微型元件结构 |
FR3105877A1 (fr) | 2019-12-30 | 2021-07-02 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procédé de connexion autoalignée d’une structure à un support, dispositif obtenu à partir d’un tel procédé, et les structure et support mis en œuvre par un tel procédé |
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US20070231961A1 (en) | 2007-10-04 |
US7432114B2 (en) | 2008-10-07 |
JP5151053B2 (ja) | 2013-02-27 |
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