JP2007250060A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2007250060A5 JP2007250060A5 JP2006070587A JP2006070587A JP2007250060A5 JP 2007250060 A5 JP2007250060 A5 JP 2007250060A5 JP 2006070587 A JP2006070587 A JP 2006070587A JP 2006070587 A JP2006070587 A JP 2006070587A JP 2007250060 A5 JP2007250060 A5 JP 2007250060A5
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- sub
- cell array
- selection switch
- cell arrays
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003491 array Methods 0.000 claims 10
- 239000004065 semiconductor Substances 0.000 claims 6
- 230000003213 activating effect Effects 0.000 claims 2
- 230000004044 response Effects 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006070587A JP2007250060A (ja) | 2006-03-15 | 2006-03-15 | 半導体記憶装置 |
| US11/724,213 US7529144B2 (en) | 2006-03-15 | 2007-03-15 | Hierarchical semiconductor memory device capable of carrying out a disturb refresh test on a memory array basis |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006070587A JP2007250060A (ja) | 2006-03-15 | 2006-03-15 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007250060A JP2007250060A (ja) | 2007-09-27 |
| JP2007250060A5 true JP2007250060A5 (enExample) | 2009-03-19 |
Family
ID=38517657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006070587A Pending JP2007250060A (ja) | 2006-03-15 | 2006-03-15 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7529144B2 (enExample) |
| JP (1) | JP2007250060A (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI360880B (en) * | 2008-06-10 | 2012-03-21 | Promos Technologies Inc | Leakage test method for dynamic random access memo |
| US8699255B2 (en) * | 2012-04-01 | 2014-04-15 | Nanya Technology Corp. | Memory array with hierarchical bit line structure |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0141432B1 (ko) * | 1993-10-01 | 1998-07-15 | 기다오까 다까시 | 반도체 기억장치 |
| US5519659A (en) * | 1993-10-01 | 1996-05-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test |
| JP2001076500A (ja) * | 1999-06-28 | 2001-03-23 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP3415502B2 (ja) * | 1999-07-30 | 2003-06-09 | Ｎｅｃエレクトロニクス株式会社 | 半導体記憶装置 |
| JP3845051B2 (ja) * | 2002-09-11 | 2006-11-15 | 株式会社東芝 | 不揮発性半導体メモリ |
| JP2005310303A (ja) * | 2004-04-23 | 2005-11-04 | Toshiba Corp | 半導体記憶装置及びそのテスト方法 |
-
2006
- 2006-03-15 JP JP2006070587A patent/JP2007250060A/ja active Pending
-
2007
- 2007-03-15 US US11/724,213 patent/US7529144B2/en active Active