JP2007250060A - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP2007250060A
JP2007250060A JP2006070587A JP2006070587A JP2007250060A JP 2007250060 A JP2007250060 A JP 2007250060A JP 2006070587 A JP2006070587 A JP 2006070587A JP 2006070587 A JP2006070587 A JP 2006070587A JP 2007250060 A JP2007250060 A JP 2007250060A
Authority
JP
Japan
Prior art keywords
memory cell
bit line
sub
cell array
selection switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006070587A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007250060A5 (enExample
Inventor
Hiroyuki Sadakata
博之 貞方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2006070587A priority Critical patent/JP2007250060A/ja
Priority to US11/724,213 priority patent/US7529144B2/en
Publication of JP2007250060A publication Critical patent/JP2007250060A/ja
Publication of JP2007250060A5 publication Critical patent/JP2007250060A5/ja
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
JP2006070587A 2006-03-15 2006-03-15 半導体記憶装置 Pending JP2007250060A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006070587A JP2007250060A (ja) 2006-03-15 2006-03-15 半導体記憶装置
US11/724,213 US7529144B2 (en) 2006-03-15 2007-03-15 Hierarchical semiconductor memory device capable of carrying out a disturb refresh test on a memory array basis

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006070587A JP2007250060A (ja) 2006-03-15 2006-03-15 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2007250060A true JP2007250060A (ja) 2007-09-27
JP2007250060A5 JP2007250060A5 (enExample) 2009-03-19

Family

ID=38517657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006070587A Pending JP2007250060A (ja) 2006-03-15 2006-03-15 半導体記憶装置

Country Status (2)

Country Link
US (1) US7529144B2 (enExample)
JP (1) JP2007250060A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI360880B (en) * 2008-06-10 2012-03-21 Promos Technologies Inc Leakage test method for dynamic random access memo
US8699255B2 (en) * 2012-04-01 2014-04-15 Nanya Technology Corp. Memory array with hierarchical bit line structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001043684A (ja) * 1999-07-30 2001-02-16 Nec Corp 半導体記憶装置
JP2004103161A (ja) * 2002-09-11 2004-04-02 Toshiba Corp 不揮発性半導体メモリ
JP2005310303A (ja) * 2004-04-23 2005-11-04 Toshiba Corp 半導体記憶装置及びそのテスト方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0141432B1 (ko) * 1993-10-01 1998-07-15 기다오까 다까시 반도체 기억장치
US5519659A (en) * 1993-10-01 1996-05-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test
JP2001076500A (ja) * 1999-06-28 2001-03-23 Mitsubishi Electric Corp 半導体記憶装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001043684A (ja) * 1999-07-30 2001-02-16 Nec Corp 半導体記憶装置
JP2004103161A (ja) * 2002-09-11 2004-04-02 Toshiba Corp 不揮発性半導体メモリ
JP2005310303A (ja) * 2004-04-23 2005-11-04 Toshiba Corp 半導体記憶装置及びそのテスト方法

Also Published As

Publication number Publication date
US20070217261A1 (en) 2007-09-20
US7529144B2 (en) 2009-05-05

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