JP2007180077A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2007180077A
JP2007180077A JP2005373734A JP2005373734A JP2007180077A JP 2007180077 A JP2007180077 A JP 2007180077A JP 2005373734 A JP2005373734 A JP 2005373734A JP 2005373734 A JP2005373734 A JP 2005373734A JP 2007180077 A JP2007180077 A JP 2007180077A
Authority
JP
Japan
Prior art keywords
lead
chip
semiconductor device
tab
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005373734A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007180077A5 (https=
Inventor
Toshio Sasaki
敏夫 佐々木
Koichiro Ishibashi
孝一郎 石橋
Fujio Ito
富士夫 伊藤
Yoshihiko Yasu
義彦 安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2005373734A priority Critical patent/JP2007180077A/ja
Publication of JP2007180077A publication Critical patent/JP2007180077A/ja
Publication of JP2007180077A5 publication Critical patent/JP2007180077A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP2005373734A 2005-12-27 2005-12-27 半導体装置 Pending JP2007180077A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005373734A JP2007180077A (ja) 2005-12-27 2005-12-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005373734A JP2007180077A (ja) 2005-12-27 2005-12-27 半導体装置

Publications (2)

Publication Number Publication Date
JP2007180077A true JP2007180077A (ja) 2007-07-12
JP2007180077A5 JP2007180077A5 (https=) 2009-02-12

Family

ID=38305004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005373734A Pending JP2007180077A (ja) 2005-12-27 2005-12-27 半導体装置

Country Status (1)

Country Link
JP (1) JP2007180077A (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009044114A (ja) * 2007-07-19 2009-02-26 Renesas Technology Corp 半導体装置及びその製造方法
JP2010016054A (ja) * 2008-07-01 2010-01-21 Renesas Technology Corp 半導体装置およびその製造方法
JP2010186831A (ja) * 2009-02-10 2010-08-26 Toshiba Corp 半導体装置
JP2011040573A (ja) * 2009-08-11 2011-02-24 Renesas Electronics Corp 半導体装置の製造方法
CN104103534A (zh) * 2013-04-02 2014-10-15 瑞萨电子株式会社 半导体器件制造方法和半导体器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252328A (ja) * 1993-02-23 1994-09-09 Mitsubishi Electric Corp 半導体素子搭載用のリードフレーム
JP2005303222A (ja) * 2004-04-16 2005-10-27 Renesas Technology Corp 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252328A (ja) * 1993-02-23 1994-09-09 Mitsubishi Electric Corp 半導体素子搭載用のリードフレーム
JP2005303222A (ja) * 2004-04-16 2005-10-27 Renesas Technology Corp 半導体装置およびその製造方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009044114A (ja) * 2007-07-19 2009-02-26 Renesas Technology Corp 半導体装置及びその製造方法
TWI452663B (zh) * 2007-07-19 2014-09-11 瑞薩電子股份有限公司 Semiconductor device and manufacturing method thereof
TWI514534B (zh) * 2007-07-19 2015-12-21 瑞薩電子股份有限公司 Semiconductor device and manufacturing method thereof
JP2010016054A (ja) * 2008-07-01 2010-01-21 Renesas Technology Corp 半導体装置およびその製造方法
JP2010186831A (ja) * 2009-02-10 2010-08-26 Toshiba Corp 半導体装置
KR101121842B1 (ko) * 2009-02-10 2012-03-21 가부시끼가이샤 도시바 반도체 장치
US8288858B2 (en) 2009-02-10 2012-10-16 Kabushiki Kaisha Toshiba Semiconductor device
TWI427749B (zh) * 2009-02-10 2014-02-21 東芝股份有限公司 Semiconductor device
JP2011040573A (ja) * 2009-08-11 2011-02-24 Renesas Electronics Corp 半導体装置の製造方法
CN104103534A (zh) * 2013-04-02 2014-10-15 瑞萨电子株式会社 半导体器件制造方法和半导体器件
JP2014203879A (ja) * 2013-04-02 2014-10-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置

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