JP2007180077A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2007180077A JP2007180077A JP2005373734A JP2005373734A JP2007180077A JP 2007180077 A JP2007180077 A JP 2007180077A JP 2005373734 A JP2005373734 A JP 2005373734A JP 2005373734 A JP2005373734 A JP 2005373734A JP 2007180077 A JP2007180077 A JP 2007180077A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- chip
- semiconductor device
- tab
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005373734A JP2007180077A (ja) | 2005-12-27 | 2005-12-27 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005373734A JP2007180077A (ja) | 2005-12-27 | 2005-12-27 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007180077A true JP2007180077A (ja) | 2007-07-12 |
| JP2007180077A5 JP2007180077A5 (enExample) | 2009-02-12 |
Family
ID=38305004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005373734A Pending JP2007180077A (ja) | 2005-12-27 | 2005-12-27 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2007180077A (enExample) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009044114A (ja) * | 2007-07-19 | 2009-02-26 | Renesas Technology Corp | 半導体装置及びその製造方法 |
| JP2010016054A (ja) * | 2008-07-01 | 2010-01-21 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP2010186831A (ja) * | 2009-02-10 | 2010-08-26 | Toshiba Corp | 半導体装置 |
| JP2011040573A (ja) * | 2009-08-11 | 2011-02-24 | Renesas Electronics Corp | 半導体装置の製造方法 |
| CN104103534A (zh) * | 2013-04-02 | 2014-10-15 | 瑞萨电子株式会社 | 半导体器件制造方法和半导体器件 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06252328A (ja) * | 1993-02-23 | 1994-09-09 | Mitsubishi Electric Corp | 半導体素子搭載用のリードフレーム |
| JP2005303222A (ja) * | 2004-04-16 | 2005-10-27 | Renesas Technology Corp | 半導体装置およびその製造方法 |
-
2005
- 2005-12-27 JP JP2005373734A patent/JP2007180077A/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06252328A (ja) * | 1993-02-23 | 1994-09-09 | Mitsubishi Electric Corp | 半導体素子搭載用のリードフレーム |
| JP2005303222A (ja) * | 2004-04-16 | 2005-10-27 | Renesas Technology Corp | 半導体装置およびその製造方法 |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009044114A (ja) * | 2007-07-19 | 2009-02-26 | Renesas Technology Corp | 半導体装置及びその製造方法 |
| TWI452663B (zh) * | 2007-07-19 | 2014-09-11 | 瑞薩電子股份有限公司 | Semiconductor device and manufacturing method thereof |
| TWI514534B (zh) * | 2007-07-19 | 2015-12-21 | 瑞薩電子股份有限公司 | Semiconductor device and manufacturing method thereof |
| JP2010016054A (ja) * | 2008-07-01 | 2010-01-21 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP2010186831A (ja) * | 2009-02-10 | 2010-08-26 | Toshiba Corp | 半導体装置 |
| KR101121842B1 (ko) * | 2009-02-10 | 2012-03-21 | 가부시끼가이샤 도시바 | 반도체 장치 |
| US8288858B2 (en) | 2009-02-10 | 2012-10-16 | Kabushiki Kaisha Toshiba | Semiconductor device |
| TWI427749B (zh) * | 2009-02-10 | 2014-02-21 | 東芝股份有限公司 | Semiconductor device |
| JP2011040573A (ja) * | 2009-08-11 | 2011-02-24 | Renesas Electronics Corp | 半導体装置の製造方法 |
| CN104103534A (zh) * | 2013-04-02 | 2014-10-15 | 瑞萨电子株式会社 | 半导体器件制造方法和半导体器件 |
| JP2014203879A (ja) * | 2013-04-02 | 2014-10-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
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