JP2007173484A5 - - Google Patents

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Publication number
JP2007173484A5
JP2007173484A5 JP2005368635A JP2005368635A JP2007173484A5 JP 2007173484 A5 JP2007173484 A5 JP 2007173484A5 JP 2005368635 A JP2005368635 A JP 2005368635A JP 2005368635 A JP2005368635 A JP 2005368635A JP 2007173484 A5 JP2007173484 A5 JP 2007173484A5
Authority
JP
Japan
Prior art keywords
wiring
semiconductor device
level
layer
extends
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005368635A
Other languages
English (en)
Japanese (ja)
Other versions
JP5296963B2 (ja
JP2007173484A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2005368635A priority Critical patent/JP5296963B2/ja
Priority claimed from JP2005368635A external-priority patent/JP5296963B2/ja
Priority to US11/612,840 priority patent/US7683490B2/en
Publication of JP2007173484A publication Critical patent/JP2007173484A/ja
Publication of JP2007173484A5 publication Critical patent/JP2007173484A5/ja
Application granted granted Critical
Publication of JP5296963B2 publication Critical patent/JP5296963B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2005368635A 2005-12-21 2005-12-21 多層配線半導体集積回路、半導体装置 Expired - Fee Related JP5296963B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005368635A JP5296963B2 (ja) 2005-12-21 2005-12-21 多層配線半導体集積回路、半導体装置
US11/612,840 US7683490B2 (en) 2005-12-21 2006-12-19 Semiconductor integrated circuit and semiconductor device having multilayer interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005368635A JP5296963B2 (ja) 2005-12-21 2005-12-21 多層配線半導体集積回路、半導体装置

Publications (3)

Publication Number Publication Date
JP2007173484A JP2007173484A (ja) 2007-07-05
JP2007173484A5 true JP2007173484A5 (enExample) 2009-11-19
JP5296963B2 JP5296963B2 (ja) 2013-09-25

Family

ID=38172515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005368635A Expired - Fee Related JP5296963B2 (ja) 2005-12-21 2005-12-21 多層配線半導体集積回路、半導体装置

Country Status (2)

Country Link
US (1) US7683490B2 (enExample)
JP (1) JP5296963B2 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116997179B (zh) * 2022-04-24 2025-05-02 长鑫存储技术有限公司 半导体结构及其形成方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5014110A (en) * 1988-06-03 1991-05-07 Mitsubishi Denki Kabushiki Kaisha Wiring structures for semiconductor memory device
JPH0319257A (ja) 1989-06-15 1991-01-28 Hitachi Ltd 半導体集積回路装置
US5864181A (en) * 1993-09-15 1999-01-26 Micron Technology, Inc. Bi-level digit line architecture for high density DRAMs
US5670815A (en) * 1994-07-05 1997-09-23 Motorola, Inc. Layout for noise reduction on a reference voltage
EP0697735B1 (en) * 1994-08-15 2002-03-27 International Business Machines Corporation Single twist layout and method for paired line conductors of integrated circuits
US5894142A (en) * 1996-12-11 1999-04-13 Hewlett-Packard Company Routing for integrated circuits
JPH11214519A (ja) * 1998-01-20 1999-08-06 Matsushita Electric Ind Co Ltd 集積回路素子および集積回路素子における配線方法
JP4501164B2 (ja) * 1998-05-01 2010-07-14 ソニー株式会社 半導体記憶装置
JP2001168195A (ja) 1999-12-06 2001-06-22 Matsushita Electric Ind Co Ltd 多層配線半導体集積回路
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
JP2003152014A (ja) * 2001-11-09 2003-05-23 Shinko Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
JP2004178704A (ja) * 2002-11-27 2004-06-24 Renesas Technology Corp 半導体回路装置
US7505321B2 (en) * 2002-12-31 2009-03-17 Sandisk 3D Llc Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
JP4405865B2 (ja) * 2004-06-24 2010-01-27 富士通マイクロエレクトロニクス株式会社 多層配線構造の製造方法及びｆｉｂ装置

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