JP2007142392A - 方法、半導体構造(準自己整合ソース/ドレインフィンfetプロセス) - Google Patents
方法、半導体構造(準自己整合ソース/ドレインフィンfetプロセス) Download PDFInfo
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Abstract
【解決手段】具体的には本発明は、複数のフィンFETデバイスを含む半導体構造を形成する方法であって、長方形のパターンを形成して相対的に細いフィンを画定する際に、これを横切るマスクを、化学的酸化物除去(COR)プロセスとともに使用する方法を提供する。この方法はさらに、シリコンを含む選択的な材料の使用によって隣接するフィンどうしを合併させるステップを含む。本発明はさらに、本発明の方法を利用して形成された半導体構造に関する。
【選択図】図9
Description
半導体基板の表面の酸化物ハードマスクの上に窒化物層を含むパターン形成された複数の材料スタックと、前記パターン形成された複数の材料スタックの上を横切るパターン形成された複数のフォトマスクとを含む構造を用意するステップと、
少なくとも、前記パターン形成されたフォトマスクによって保護されていないそれぞれの材料スタックの前記酸化物ハードマスクの露出した側壁を横方向にエッチングする化学的酸化物除去ステップを実行するステップと、
パターン形成された複数のフォトマスクを除去して、横方向にエッチングされた酸化物ハードマスクを前記窒化物層の下に含むパターン形成された材料スタックを露出させるステップと、
横方向にエッチングされた酸化物ハードマスクに対して選択的である異方性エッチング・プロセスを実行して、前記窒化物層と、前記横方向にエッチングされた酸化物ハードマスクによって保護されていない前記半導体基板の半導体材料の少なくとも上部とを除去し、それによってフィンを形成するステップと、
前記フィンの上を横切る複数のゲート領域を形成するステップと
を含む方法を提供する。
半導体基板の表面に位置する複数のフィンFETデバイスであって、それぞれが、自体の中間部分に比べて相対的に幅が広い端部を有する高くなった半導体層と、前記中間部分を横切るゲート領域と、前記相対的に幅が広い端部の内部に形成されたソース/ドレイン領域とを含むフィンFETデバイスと、
前記高くなった半導体層間に位置し、それぞれの高くなった半導体層を接合するSiを含む材料と
を含む。
12 下部半導体層
14 埋込み絶縁層
16 上部半導体層
18 酸化物ハードマスク
20 窒化物層
22 第1のフォトマスク
24 材料スタック
26 第2のフォトマスク
28 ゲート領域
29 ゲート誘電体
30 ゲート電極
32 ゲート・スペーサ
34 Siを含む単結晶材料
100 構造
102 フィンFETデバイス
104 フィン
Claims (20)
- 半導体構造を形成する方法であって、
半導体基板の表面の酸化物ハードマスクの上に窒化物層を含むパターン形成された複数の材料スタックと、前記パターン形成された複数の材料スタックの上を横切るパターン形成された複数のフォトマスクとを含む構造を用意するステップと、
少なくとも、前記パターン形成されたフォトマスクによって保護されていないそれぞれの材料スタックの前記酸化物ハードマスクの露出した側壁を横方向にエッチングする化学的酸化物除去ステップを実行するステップと、
前記パターン形成された複数のフォトマスクを除去して、横方向にエッチングされた酸化物ハードマスクを前記窒化物層の下に含むパターン形成された材料スタックを露出させるステップと、
前記横方向にエッチングされた酸化物ハードマスクに対して選択的であるハードマスクに対して選択的である異方性エッチング・プロセスを実行して、前記窒化物層と、前記横方向にエッチングされた酸化物ハードマスクによって保護されていない前記半導体基板の半導体材料の少なくとも上部とを除去し、それによってフィンを形成するステップと、
前記フィンの上を横切る複数のゲート領域を形成するステップと
を含む方法。 - それぞれの前記フィン間に、Siを含む材料を、隣接するフィンを接合するように形成するステップをさらに含む、請求項1に記載の方法。
- 前記Siを含む材料が、単結晶のSi、SiGeおよびSiGeCのうちの1つを含む、請求項2に記載の方法。
- 前記半導体基板がSOIまたはバルク半導体である、請求項1に記載の方法。
- 前記化学的酸化物除去ステップが、HFとアンモニアの気体または蒸気混合物を利用するステップを含み、HFとアンモニアの比が1:10から10:1である、請求項1に記載の方法。
- 前記横方向にエッチングされた酸化物ハードマスクを除去して、前記横方向にエッチングされた酸化物ハードマスクによって以前に保護されていた前記半導体基板の前記半導体材料の上部を露出させるステップをさらに含む、請求項1に記載の方法。
- フィンがそれぞれ、自体の中間部分に比べて相対的に幅が広い端部を有し、前記ゲート領域が前記中間部分を横切るように形成され、前記相対的に幅が広い端部の内部にソース/ドレイン領域が形成される、請求項1に記載の方法。
- それぞれのフィンの端部の内部にソース/ドレイン領域を形成するステップをさらに含み、それぞれのフィンの前記端部が実質的に正方形である、請求項1に記載の方法。
- 半導体構造を形成する方法であって、
SOI基板の上部半導体層の表面の酸化物ハードマスクの上に窒化物層を含むパターン形成された複数の材料スタックと、前記パターン形成された複数の材料スタックの上を横切るパターン形成された複数のフォトマスクとを用意するステップと、
少なくとも、前記パターン形成されたフォトマスクによって保護されていないそれぞれの材料スタックの前記酸化物ハードマスクの露出した側壁を横方向にエッチングする化学的酸化物除去ステップを実行するステップと、
前記パターン形成された複数のフォトマスクを除去して、横方向にエッチングされた酸化物ハードマスクを前記窒化物層の下に含むパターン形成された材料スタックを露出させるステップと、
前記横方向にエッチングされた酸化物ハードマスクに対して選択的である異方性エッチング・プロセスを実行して、前記窒化物層と、前記横方向にエッチングされた酸化物ハードマスクによって保護されていない前記SOI基板の少なくとも前記上部半導体層とを、前記SOI基板の埋込み絶縁層の表面まで除去するステップと、
前記横方向にエッチングされた酸化物ハードマスクを除去して、前記横方向にエッチングされた酸化物ハードマスクによって以前に保護されていた前記SOI基板の前記上部半導体層の上部を露出させ、さらに前記埋込み絶縁層の露出した部分を除去するステップであって、前記横方向にエッチングされた酸化物ハードマスクによって以前に保護されていた前記SOI基板の前記露出させた上部半導体層の部分がフィンを画定するステップと、
前記フィンの上を横切る複数のゲート領域を形成するステップと
を含む方法。 - それぞれの前記フィン間に、Siを含む材料を、隣接するフィンを接合するように形成するステップをさらに含む、請求項9に記載の方法。
- 前記化学的酸化物除去ステップが、HFとアンモニアの気体または蒸気混合物を利用するステップを含み、HFとアンモニアの比が1:10から10:1である、請求項9に記載の方法。
- それぞれのゲート領域の周囲にゲート・スペーサを形成するステップをさらに含む、請求項9に記載の半導体構造。
- 半導体基板の表面に位置する複数のフィンFETデバイスであって、それぞれが、自体の中間部分に比べて相対的に幅が広い端部を有する高くなった半導体層と、前記中間部分を横切るゲート領域と、前記相対的に幅が広い端部の内部に形成されたソース/ドレイン領域とを含むフィンFETデバイスと、
前記高くなった半導体層間に位置し、それぞれの高くなった半導体層を接合するSiを含む材料と
を含む半導体構造。 - 前記高くなった半導体層がSOI基板の上部半導体層であり、前記SOI基板が、パターン形成されまたはされていない埋込み絶縁層ならびにパターン形成されていない下部半導体層を含む、請求項13に記載の半導体構造。
- 前記高くなった半導体層がSiを含む半導体であり、前記埋込み絶縁層が酸化物である、請求項14に記載の半導体構造。
- ゲート領域がそれぞれゲート誘電体およびゲート電極を含む、請求項13に記載の半導体構造。
- それぞれのゲート領域の周囲に配置されたゲート・スペーサをさらに含む、請求項13に記載の半導体構造。
- 前記高くなった半導体層がバルク半導体基板の上部表層である、請求項13に記載の半導体構造。
- 前記Siを含む材料が、単結晶のSi、SiGeおよびSiGeCのうちの1つを含む、請求項13に記載の半導体構造。
- 前記高くなった半導体層の前記端部が実質的に正方形である、請求項13に記載の半導体構造。
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US11/164215 | 2005-11-15 |
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CN100485908C (zh) | 2009-05-06 |
US7309626B2 (en) | 2007-12-18 |
US20080042202A1 (en) | 2008-02-21 |
JP5128110B2 (ja) | 2013-01-23 |
US20070108536A1 (en) | 2007-05-17 |
CN1967812A (zh) | 2007-05-23 |
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