JP2006525750A - 波形グリッチ防止方法 - Google Patents

波形グリッチ防止方法 Download PDF

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Publication number
JP2006525750A
JP2006525750A JP2006509997A JP2006509997A JP2006525750A JP 2006525750 A JP2006525750 A JP 2006525750A JP 2006509997 A JP2006509997 A JP 2006509997A JP 2006509997 A JP2006509997 A JP 2006509997A JP 2006525750 A JP2006525750 A JP 2006525750A
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JP
Japan
Prior art keywords
periodic waveform
enable signal
phase
delay
gate
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP2006509997A
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English (en)
Japanese (ja)
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JP2006525750A5 (enExample
Inventor
エドワード ポール ローラー
デービッド マイケル チャーネスキー
Original Assignee
イーストマン コダック カンパニー
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Application filed by イーストマン コダック カンパニー filed Critical イーストマン コダック カンパニー
Publication of JP2006525750A publication Critical patent/JP2006525750A/ja
Publication of JP2006525750A5 publication Critical patent/JP2006525750A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP2006509997A 2003-04-30 2004-04-14 波形グリッチ防止方法 Pending JP2006525750A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/426,263 US6882206B2 (en) 2003-04-30 2003-04-30 Enabling method to prevent glitches in waveform of arbitrary phase
PCT/US2004/011415 WO2004100373A1 (en) 2003-04-30 2004-04-14 Enabling method to prevent glitches in waveform

Publications (2)

Publication Number Publication Date
JP2006525750A true JP2006525750A (ja) 2006-11-09
JP2006525750A5 JP2006525750A5 (enExample) 2007-06-14

Family

ID=33309828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006509997A Pending JP2006525750A (ja) 2003-04-30 2004-04-14 波形グリッチ防止方法

Country Status (4)

Country Link
US (1) US6882206B2 (enExample)
EP (1) EP1618660B1 (enExample)
JP (1) JP2006525750A (enExample)
WO (1) WO2004100373A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010035225A (ja) * 2009-11-10 2010-02-12 Epson Imaging Devices Corp クロック発生回路

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004063199B4 (de) * 2004-12-23 2010-11-25 Atmel Automotive Gmbh Pulsgenerator und Verfahren zur Erzeugung einer Pulsfolge
EP1705815B1 (en) * 2005-03-22 2011-08-24 Infineon Technologies AG A digital clock switching means
US9337820B1 (en) * 2015-02-23 2016-05-10 Qualcomm Incorporated Pulse width recovery in clock dividers

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62180607A (ja) * 1986-02-04 1987-08-07 Fujitsu Ltd 半導体集積回路
JPH02296410A (ja) * 1989-05-11 1990-12-07 Mitsubishi Electric Corp 遅延回路
JPH04159810A (ja) * 1990-10-23 1992-06-03 Fujitsu Ltd 時間自動調整回路
JPH05233091A (ja) * 1992-02-18 1993-09-10 Nec Corp クロック発生回路
JPH06326574A (ja) * 1993-05-18 1994-11-25 Mega Chips:Kk 制御信号発生回路，パルス幅変調回路，遅延制御回路およびクロック発生回路
JPH07264023A (ja) * 1994-03-18 1995-10-13 Sony Corp ディレー用デバイス及び遅延位相出力装置
JPH11218564A (ja) * 1998-01-30 1999-08-10 Ando Electric Co Ltd タイミング信号発生回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574753A (en) * 1993-12-23 1996-11-12 Unisys Corporation Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs
JP3292584B2 (ja) * 1994-04-08 2002-06-17 株式会社東芝 タイミング発生装置
US5481230A (en) 1994-11-14 1996-01-02 Tektronix, Inc. Phase modulator having individually placed edges
US5652536A (en) * 1995-09-25 1997-07-29 Cirrus Logic, Inc. Non-glitch clock switching circuit
US5808486A (en) * 1997-04-28 1998-09-15 Ag Communication Systems Corporation Glitch free clock enable circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62180607A (ja) * 1986-02-04 1987-08-07 Fujitsu Ltd 半導体集積回路
JPH02296410A (ja) * 1989-05-11 1990-12-07 Mitsubishi Electric Corp 遅延回路
JPH04159810A (ja) * 1990-10-23 1992-06-03 Fujitsu Ltd 時間自動調整回路
JPH05233091A (ja) * 1992-02-18 1993-09-10 Nec Corp クロック発生回路
JPH06326574A (ja) * 1993-05-18 1994-11-25 Mega Chips:Kk 制御信号発生回路，パルス幅変調回路，遅延制御回路およびクロック発生回路
JPH07264023A (ja) * 1994-03-18 1995-10-13 Sony Corp ディレー用デバイス及び遅延位相出力装置
JPH11218564A (ja) * 1998-01-30 1999-08-10 Ando Electric Co Ltd タイミング信号発生回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010035225A (ja) * 2009-11-10 2010-02-12 Epson Imaging Devices Corp クロック発生回路

Also Published As

Publication number Publication date
WO2004100373A1 (en) 2004-11-18
US6882206B2 (en) 2005-04-19
EP1618660A1 (en) 2006-01-25
US20040217796A1 (en) 2004-11-04
EP1618660B1 (en) 2013-06-12

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