Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
  • H03K2005/0015—Layout of the delay element
  • H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks

Definitions

• This invention relates generally to electronic imaging systems and, more particularly, to starting and stopping critical systems clocks without creating glitches or spurious pulses.
• a series of logic-level pulses can typically be created by performing a logical AND of a continuously running pulse train with a positive logic enable signal.
• the enable signal should transition from low to high and high to low when the pulse train is low.
• the phase of the enable signal must be varied accordingly.
• the enable signal is typically generated by logic running from a non-adjustable system clock of fixed phase. Consequently, a mechanism is needed for varying the phase of the enable signal so that shortened pulses or glitches are not created.
• the present invention is directed to providing a mechanism for varying the phase of the enable signal.
• the invention includes a system for generating a gated periodic waveform, the system includes (a) a generator for generating a periodic waveform of adjustable phase; (b) a device for providing a delayed enable signal based on the phase of the periodic waveform so that the gated periodic waveform can be started and stopped without creating undesirable changes in the gated periodic waveform; and (c) a logic element for generating a gated periodic waveform based on the delayed enable signal and the periodic waveform of adjustable phase.
• Fig. 1 is a timing diagram showing the various clocks and phases used in the present invention
• Fig. 2 is a logic diagram showing the logic used to create a gated pulse train of the present invention
• Fig. 3 is an alternative embodiment of Fig. 2; and Fig. 4 is a timing diagram for Fig. 2.
• Fig. 1 In Fig. 1 are shown four 'core clock' phases each having a 90- degree phase separation. These core clocks are used as inputs to an enable delay logic 10 shown in Fig. 2. Also shown in Fig. 1 are 64 free running clock phases, "PULSE_TRAIN_PHASE_0" through “PULSE_TRAIN_PHASE_63”, where “PULSE_TRAIN_PHASE_0” is phase aligned with the "CORE_CLK_0", and each successive phase of "PULSE_TRAIN_PH ASE_0" through
• PULSE_TRAIN_PHASE_63 is shifted by l/64 th of the clock period from the previous phase. These will be used as inputs to a multiplexer 20 shown in Fig. 2.
• Fig. 2 shows delay logic 10 for an "ENABLE” signal which is generated externally for producing a "GATED_PULSE_TRAIN” signal.
• the control bus 30 is used by the multiplexer 20 to select a phase of the pulse train to be passed by the multiplexer 20, and is also used by the gating control logic 40 to enable one of the delay paths (Gate 0, Gate 16, Gate 32, Gate 48 and Gate 56). It is instructive to note that only one of these paths is enabled, and the others are disabled and drive a logic 0 to the OR gate 60.
• the delay path from signal "GATE_0” uses AND gate 70 to allow the system enable signal to pass to flip- flop 80.
• the clock for flip-flop 80 is the falling edge of "CORE_CLK_90". This delays the system enable signal by % of the clock period.
• the output of flip-flop 80 goes to OR gate 60 and then to AND gate 90 where the enabling and disabling of the selected pulse train phase is accomplished.
• the delay path from signal "GATE_16” uses AND gate 100 to allow the system enable to pass to flip-flop 110.
• the clock for flip-flop 110 is the rising edge of "CORE_CLK_0". This delays the system enable by a full clock period and correspondingly delays the enabling and disabling of the selected pulse train at AND gate 90.
• the enabling and disabling at AND gate 90 is delayed by 1.25, 1.5 and 1.75 clock periods, respectively. It is noted that the flip-flops associated with these gates function substantially similar to flip-flops 80 and 110 to create the delays and will not be discussed in detail herein.
• Fig. 3 shows another delay logic 120 for an "ENABLE” signal which is generated externally for producing a "GATED_PULSE_TRAIN” signal.
• the logic herein is similar to Fig. 2 with the exception that the delay paths are as follows.
• the delays for signal paths "Gate_0”, “Gate_16”, “Gate_32”, “Gate_48”, and “Gate_56" are 1.25, 1.5, 1.75, 2, and 2.25 clock periods respectively.
• similar components are used for the logic 20, 30, 60 and 90 in both Figs. 2 and 3.
• those skilled in the art would readily recognize how the new delays are implemented with the flip-flops shown, and as a result, it will not be discussed in detail herein.
• Fig. 4 illustrates the timing for Fig. 2.
• the "ENABLE” signal is generated externally by clocked logic (not shown) using “CORE_CLK_0".
• the "CNTLJ3US" value has resulted in the "GATE_0" signal path being selected by "GATING CONTROL LOGIC” 40.
• This causes transition of "DELAYED_ENABLE” at AND gate 90 to occur while signal “MUX_OUT” is low, thus precluding any shortened pulses or glitches when starting or stopping signal "GATED_PULSE_TRAIN".
• the invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.

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• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Pulse Circuits (AREA)
• Manipulation Of Pulses (AREA)

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• 2003
  • 2003-04-30 US US10/426,263 patent/US6882206B2/en not_active Expired - Lifetime
• 2004
  • 2004-04-14 WO PCT/US2004/011415 patent/WO2004100373A1/en not_active Ceased
  • 2004-04-14 EP EP04760541.5A patent/EP1618660B1/en not_active Expired - Lifetime
  • 2004-04-14 JP JP2006509997A patent/JP2006525750A/ja active Pending

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