JP2006524427A5 - - Google Patents

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Publication number
JP2006524427A5
JP2006524427A5 JP2006504301A JP2006504301A JP2006524427A5 JP 2006524427 A5 JP2006524427 A5 JP 2006524427A5 JP 2006504301 A JP2006504301 A JP 2006504301A JP 2006504301 A JP2006504301 A JP 2006504301A JP 2006524427 A5 JP2006524427 A5 JP 2006524427A5
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JP
Japan
Prior art keywords
wafer
burdensome
polishing
grown
reactor
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JP2006504301A
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English (en)
Japanese (ja)
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JP5065676B2 (ja
JP2006524427A (ja
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Priority claimed from DE10318284A external-priority patent/DE10318284A1/de
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Publication of JP2006524427A publication Critical patent/JP2006524427A/ja
Publication of JP2006524427A5 publication Critical patent/JP2006524427A5/ja
Application granted granted Critical
Publication of JP5065676B2 publication Critical patent/JP5065676B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2006504301A 2003-04-22 2004-04-15 基板上に歪層を製造する方法及び層構造 Expired - Lifetime JP5065676B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10318284A DE10318284A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
DE10318284.5 2003-04-22
PCT/DE2004/000780 WO2004095553A2 (de) 2003-04-22 2004-04-15 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur

Publications (3)

Publication Number Publication Date
JP2006524427A JP2006524427A (ja) 2006-10-26
JP2006524427A5 true JP2006524427A5 (enExample) 2012-03-29
JP5065676B2 JP5065676B2 (ja) 2012-11-07

Family

ID=33304880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006504301A Expired - Lifetime JP5065676B2 (ja) 2003-04-22 2004-04-15 基板上に歪層を製造する方法及び層構造

Country Status (5)

Country Link
US (1) US7416965B2 (enExample)
EP (1) EP1616346A2 (enExample)
JP (1) JP5065676B2 (enExample)
DE (1) DE10318284A1 (enExample)
WO (1) WO2004095553A2 (enExample)

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DE102004048096A1 (de) * 2004-09-30 2006-04-27 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7229901B2 (en) * 2004-12-16 2007-06-12 Wisconsin Alumni Research Foundation Fabrication of strained heterojunction structures
JP4654710B2 (ja) * 2005-02-24 2011-03-23 信越半導体株式会社 半導体ウェーハの製造方法
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2892855B1 (fr) 2005-10-28 2008-07-18 Commissariat Energie Atomique Procede de fabrication d'une structure en couches minces et structure en couches minces ainsi obtenue
KR101455404B1 (ko) * 2005-12-09 2014-10-27 세미이큅, 인코포레이티드 탄소 클러스터의 주입에 의한 반도체 디바이스의 제조를위한 시스템 및 방법
FR2896255B1 (fr) 2006-01-17 2008-05-09 Soitec Silicon On Insulator Procede d'ajustement de la contrainte d'un substrat en un materiau semi-conducteur
EP1808886A3 (fr) * 2006-01-17 2009-08-12 S.O.I.T.E.C. Silicon on Insulator Technologies Procédé d'ajustement de la contrainte d'un substrat en un matériau semi-conducteur
DE102006004870A1 (de) * 2006-02-02 2007-08-16 Siltronic Ag Halbleiterschichtstruktur und Verfahren zur Herstellung einer Halbleiterschichtstruktur
WO2007094057A1 (ja) * 2006-02-15 2007-08-23 Fujitsu Limited 光デバイス
DE102006010273B4 (de) * 2006-03-02 2010-04-15 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte, Schichtstapel und dessen Verwendung
US7514726B2 (en) * 2006-03-21 2009-04-07 The United States Of America As Represented By The Aministrator Of The National Aeronautics And Space Administration Graded index silicon geranium on lattice matched silicon geranium semiconductor alloy
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
US7494886B2 (en) 2007-01-12 2009-02-24 International Business Machines Corporation Uniaxial strain relaxation of biaxial-strained thin films using ion implantation
WO2009051835A1 (en) * 2007-10-18 2009-04-23 United States Of America As Representated By The Administrator Of The National Aeronautics And Space Administration X-ray diffraction wafer mapping method for rhombohedral super-hetero-epitaxy
US7943414B2 (en) * 2008-08-01 2011-05-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2011166129A (ja) * 2010-01-15 2011-08-25 Sumitomo Chemical Co Ltd 半導体基板、電子デバイス及び半導体基板の製造方法
US8361889B2 (en) * 2010-07-06 2013-01-29 International Business Machines Corporation Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator
DE102010046215B4 (de) * 2010-09-21 2019-01-03 Infineon Technologies Austria Ag Halbleiterkörper mit verspanntem Bereich, Elektronisches Bauelement und ein Verfahren zum Erzeugen des Halbleiterkörpers.
US8501600B2 (en) * 2010-09-27 2013-08-06 Applied Materials, Inc. Methods for depositing germanium-containing layers
US10361097B2 (en) * 2012-12-31 2019-07-23 Globalwafers Co., Ltd. Apparatus for stressing semiconductor substrates
US9614026B2 (en) 2013-03-13 2017-04-04 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices
FR3003686B1 (fr) * 2013-03-20 2016-11-04 St Microelectronics Crolles 2 Sas Procede de formation d'une couche de silicium contraint
US9305781B1 (en) 2015-04-30 2016-04-05 International Business Machines Corporation Structure and method to form localized strain relaxed SiGe buffer layer
CN111733378B (zh) * 2020-05-15 2022-12-13 中国兵器科学研究院宁波分院 一种钢表面的涂层结构及其制备方法

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US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
DE19802977A1 (de) * 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
US6326667B1 (en) * 1999-09-09 2001-12-04 Kabushiki Kaisha Toshiba Semiconductor devices and methods for producing semiconductor devices
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
ATE346410T1 (de) * 2000-08-04 2006-12-15 Amberwave Systems Corp Siliziumwafer mit monolithischen optoelektronischen komponenten
US6573126B2 (en) * 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
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JP3875040B2 (ja) * 2001-05-17 2007-01-31 シャープ株式会社 半導体基板及びその製造方法ならびに半導体装置及びその製造方法
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
JP2003008022A (ja) * 2001-06-20 2003-01-10 Mitsubishi Materials Silicon Corp 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
JP4854871B2 (ja) * 2001-06-20 2012-01-18 株式会社Ｓｕｍｃｏ 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
US6562703B1 (en) * 2002-03-13 2003-05-13 Sharp Laboratories Of America, Inc. Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content
DE10218381A1 (de) 2002-04-24 2004-02-26 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer oder mehrerer einkristalliner Schichten mit jeweils unterschiedlicher Gitterstruktur in einer Ebene einer Schichtenfolge
US6972245B2 (en) 2002-05-15 2005-12-06 The Regents Of The University Of California Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures
US6841457B2 (en) * 2002-07-16 2005-01-11 International Business Machines Corporation Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion
DE10310740A1 (de) 2003-03-10 2004-09-30 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen
JP2004281764A (ja) * 2003-03-17 2004-10-07 Seiko Epson Corp 半導体装置およびその製造方法
DE10318283A1 (de) * 2003-04-22 2004-11-25 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7049660B2 (en) * 2003-05-30 2006-05-23 International Business Machines Corporation High-quality SGOI by oxidation near the alloy melting temperature

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