JP2006517343A - 引張歪み基板を有するｍｏｓｆｅｔデバイスおよびその作製方法 - Google Patents

引張歪み基板を有するｍｏｓｆｅｔデバイスおよびその作製方法 Download PDF

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JP2006517343A
JP2006517343A JP2006502832A JP2006502832A JP2006517343A JP 2006517343 A JP2006517343 A JP 2006517343A JP 2006502832 A JP2006502832 A JP 2006502832A JP 2006502832 A JP2006502832 A JP 2006502832A JP 2006517343 A JP2006517343 A JP 2006517343A
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layer
gate
silicon
deposition
spacer
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JP2006517343A5 (enExample
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バン エヌジーオー ミン
アール． ベセル ポール
リン ミン−レン
ワン ハイホン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2006502832A 2003-01-17 2004-01-13 引張歪み基板を有するｍｏｓｆｅｔデバイスおよびその作製方法 Pending JP2006517343A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/346,617 US7001837B2 (en) 2003-01-17 2003-01-17 Semiconductor with tensile strained substrate and method of making the same
PCT/US2004/000981 WO2004068586A1 (en) 2003-01-17 2004-01-13 Mosfet device with tensile strained substrate and method of making the same

Publications (2)

Publication Number Publication Date
JP2006517343A true JP2006517343A (ja) 2006-07-20
JP2006517343A5 JP2006517343A5 (enExample) 2009-01-15

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JP2006502832A Pending JP2006517343A (ja) 2003-01-17 2004-01-13 引張歪み基板を有するｍｏｓｆｅｔデバイスおよびその作製方法

Country Status (7)

Country Link
US (2) US7001837B2 (enExample)
JP (1) JP2006517343A (enExample)
KR (1) KR101023208B1 (enExample)
CN (1) CN1762056B (enExample)
DE (1) DE112004000146B4 (enExample)
GB (1) GB2411768B (enExample)
WO (1) WO2004068586A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008504677A (ja) * 2004-06-24 2008-02-14 インターナショナル・ビジネス・マシーンズ・コーポレーション 改良した歪みシリコンｃｍｏｓデバイスおよび方法

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US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6940089B2 (en) 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US7301180B2 (en) 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US6916727B2 (en) * 2001-06-21 2005-07-12 Massachusetts Institute Of Technology Enhancement of P-type metal-oxide-semiconductor field effect transistors
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US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US7138649B2 (en) * 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
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US20060099763A1 (en) * 2004-10-28 2006-05-11 Yi-Cheng Liu Method of manufacturing semiconductor mos transistor device
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US7892928B2 (en) * 2007-03-23 2011-02-22 International Business Machines Corporation Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers
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US8232186B2 (en) * 2008-05-29 2012-07-31 International Business Machines Corporation Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure
JP5381350B2 (ja) * 2009-06-03 2014-01-08 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US8236709B2 (en) 2009-07-29 2012-08-07 International Business Machines Corporation Method of fabricating a device using low temperature anneal processes, a device and design structure
TWI419324B (zh) * 2009-11-27 2013-12-11 Univ Nat Chiao Tung 具有三五族通道及四族源汲極之半導體裝置及其製造方法
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Publication number Priority date Publication date Assignee Title
JP2008504677A (ja) * 2004-06-24 2008-02-14 インターナショナル・ビジネス・マシーンズ・コーポレーション 改良した歪みシリコンｃｍｏｓデバイスおよび方法

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GB2411768A (en) 2005-09-07
US7701019B2 (en) 2010-04-20
US20060138479A1 (en) 2006-06-29
US7001837B2 (en) 2006-02-21
GB0512330D0 (en) 2005-07-27
KR101023208B1 (ko) 2011-03-18
CN1762056A (zh) 2006-04-19
DE112004000146T5 (de) 2006-02-02
US20040142545A1 (en) 2004-07-22
WO2004068586A1 (en) 2004-08-12
DE112004000146B4 (de) 2010-05-06
KR20050086961A (ko) 2005-08-30
GB2411768B (en) 2006-04-26
CN1762056B (zh) 2011-06-01

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