CN1762056B - 具有拉伸应变基片的半导体及其制备方法 - Google Patents
具有拉伸应变基片的半导体及其制备方法 Download PDFInfo
- Publication number
- CN1762056B CN1762056B CN2004800074546A CN200480007454A CN1762056B CN 1762056 B CN1762056 B CN 1762056B CN 2004800074546 A CN2004800074546 A CN 2004800074546A CN 200480007454 A CN200480007454 A CN 200480007454A CN 1762056 B CN1762056 B CN 1762056B
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- China
- Prior art keywords
- layer
- silicon
- silicon layer
- gate
- etch stop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/346,617 US7001837B2 (en) | 2003-01-17 | 2003-01-17 | Semiconductor with tensile strained substrate and method of making the same |
| US10/346,617 | 2003-01-17 | ||
| PCT/US2004/000981 WO2004068586A1 (en) | 2003-01-17 | 2004-01-13 | Mosfet device with tensile strained substrate and method of making the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1762056A CN1762056A (zh) | 2006-04-19 |
| CN1762056B true CN1762056B (zh) | 2011-06-01 |
Family
ID=32712194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2004800074546A Expired - Lifetime CN1762056B (zh) | 2003-01-17 | 2004-01-13 | 具有拉伸应变基片的半导体及其制备方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7001837B2 (enExample) |
| JP (1) | JP2006517343A (enExample) |
| KR (1) | KR101023208B1 (enExample) |
| CN (1) | CN1762056B (enExample) |
| DE (1) | DE112004000146B4 (enExample) |
| GB (1) | GB2411768B (enExample) |
| WO (1) | WO2004068586A1 (enExample) |
Families Citing this family (53)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
| US6830976B2 (en) | 2001-03-02 | 2004-12-14 | Amberwave Systems Corproation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6703688B1 (en) | 2001-03-02 | 2004-03-09 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6940089B2 (en) | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
| US7301180B2 (en) * | 2001-06-18 | 2007-11-27 | Massachusetts Institute Of Technology | Structure and method for a high-speed semiconductor device having a Ge channel layer |
| WO2003001607A1 (en) * | 2001-06-21 | 2003-01-03 | Massachusetts Institute Of Technology | Mosfets with strained semiconductor layers |
| EP1415331A2 (en) * | 2001-08-06 | 2004-05-06 | Massachusetts Institute Of Technology | Formation of planar strained layers |
| US7138649B2 (en) * | 2001-08-09 | 2006-11-21 | Amberwave Systems Corporation | Dual-channel CMOS transistors with differentially strained channels |
| US6974735B2 (en) | 2001-08-09 | 2005-12-13 | Amberwave Systems Corporation | Dual layer Semiconductor Devices |
| WO2003017336A2 (en) * | 2001-08-13 | 2003-02-27 | Amberwave Systems Corporation | Dram trench capacitor and method of making the same |
| JP2005504436A (ja) | 2001-09-21 | 2005-02-10 | アンバーウェーブ システムズ コーポレイション | 画定された不純物勾配を有するひずみ材料層を使用する半導体構造、およびその構造を製作するための方法。 |
| WO2003028106A2 (en) | 2001-09-24 | 2003-04-03 | Amberwave Systems Corporation | Rf circuits including transistors having strained material layers |
| US6657276B1 (en) * | 2001-12-10 | 2003-12-02 | Advanced Micro Devices, Inc. | Shallow trench isolation (STI) region with high-K liner and method of formation |
| US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
| WO2003105204A2 (en) * | 2002-06-07 | 2003-12-18 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
| US7074623B2 (en) | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
| US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
| US7335545B2 (en) | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
| US7307273B2 (en) | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
| US7615829B2 (en) | 2002-06-07 | 2009-11-10 | Amberwave Systems Corporation | Elevated source and drain elements for strained-channel heterojuntion field-effect transistors |
| US6946371B2 (en) | 2002-06-10 | 2005-09-20 | Amberwave Systems Corporation | Methods of fabricating semiconductor structures having epitaxially grown source and drain elements |
| US6982474B2 (en) | 2002-06-25 | 2006-01-03 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
| US7091068B1 (en) * | 2002-12-06 | 2006-08-15 | Advanced Micro Devices, Inc. | Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices |
| US20040154083A1 (en) * | 2002-12-23 | 2004-08-12 | Mcvicker Henry J. | Sports pad closure system with integrally molded hooks |
| US6960781B2 (en) * | 2003-03-07 | 2005-11-01 | Amberwave Systems Corporation | Shallow trench isolation process |
| US7303949B2 (en) * | 2003-10-20 | 2007-12-04 | International Business Machines Corporation | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture |
| US7462526B2 (en) * | 2003-11-18 | 2008-12-09 | Silicon Genesis Corporation | Method for fabricating semiconductor devices using strained silicon bearing material |
| US7053400B2 (en) * | 2004-05-05 | 2006-05-30 | Advanced Micro Devices, Inc. | Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility |
| US7321155B2 (en) * | 2004-05-06 | 2008-01-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Offset spacer formation for strained channel CMOS transistor |
| US7227205B2 (en) * | 2004-06-24 | 2007-06-05 | International Business Machines Corporation | Strained-silicon CMOS device and method |
| DE102004042167B4 (de) * | 2004-08-31 | 2009-04-02 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Ausbilden einer Halbleiterstruktur, die Transistorelemente mit unterschiedlich verspannten Kanalgebieten umfasst, und entsprechende Halbleiterstruktur |
| US20060099763A1 (en) * | 2004-10-28 | 2006-05-11 | Yi-Cheng Liu | Method of manufacturing semiconductor mos transistor device |
| US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
| US20060172556A1 (en) * | 2005-02-01 | 2006-08-03 | Texas Instruments Incorporated | Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor |
| JP2008530792A (ja) * | 2005-02-11 | 2008-08-07 | エヌエックスピー ビー ヴィ | 電子デバイスにおけるsti領域形成方法 |
| CN100446282C (zh) * | 2005-09-19 | 2008-12-24 | 深圳帝光电子有限公司 | Led光源产品 |
| US7615432B2 (en) * | 2005-11-02 | 2009-11-10 | Samsung Electronics Co., Ltd. | HDP/PECVD methods of fabricating stress nitride structures for field effect transistors |
| US7550356B2 (en) * | 2005-11-14 | 2009-06-23 | United Microelectronics Corp. | Method of fabricating strained-silicon transistors |
| US7939413B2 (en) * | 2005-12-08 | 2011-05-10 | Samsung Electronics Co., Ltd. | Embedded stressor structure and process |
| US7888214B2 (en) * | 2005-12-13 | 2011-02-15 | Globalfoundries Singapore Pte. Ltd. | Selective stress relaxation of contact etch stop layer through layout design |
| US20070158739A1 (en) * | 2006-01-06 | 2007-07-12 | International Business Machines Corporation | Higher performance CMOS on (110) wafers |
| US20080124880A1 (en) * | 2006-09-23 | 2008-05-29 | Chartered Semiconductor Manufacturing Ltd. | Fet structure using disposable spacer and stress inducing layer |
| US7897493B2 (en) * | 2006-12-08 | 2011-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inducement of strain in a semiconductor layer |
| US7892928B2 (en) * | 2007-03-23 | 2011-02-22 | International Business Machines Corporation | Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers |
| US7745847B2 (en) * | 2007-08-09 | 2010-06-29 | United Microelectronics Corp. | Metal oxide semiconductor transistor |
| US8058123B2 (en) | 2007-11-29 | 2011-11-15 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit and method of fabrication thereof |
| US20090146194A1 (en) * | 2007-12-05 | 2009-06-11 | Ecole Polytechnique Federale De Lausanne (Epfl) | Semiconductor device and method of manufacturing a semiconductor device |
| US8232186B2 (en) * | 2008-05-29 | 2012-07-31 | International Business Machines Corporation | Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure |
| JP5381350B2 (ja) * | 2009-06-03 | 2014-01-08 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| US8236709B2 (en) | 2009-07-29 | 2012-08-07 | International Business Machines Corporation | Method of fabricating a device using low temperature anneal processes, a device and design structure |
| TWI419324B (zh) * | 2009-11-27 | 2013-12-11 | Univ Nat Chiao Tung | 具有三五族通道及四族源汲極之半導體裝置及其製造方法 |
| US8865576B2 (en) * | 2011-09-29 | 2014-10-21 | Eastman Kodak Company | Producing vertical transistor having reduced parasitic capacitance |
| US8759920B2 (en) * | 2012-06-01 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6071784A (en) * | 1997-08-29 | 2000-06-06 | Advanced Micro Devices, Inc. | Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss |
| US6492216B1 (en) * | 2002-02-07 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Method of forming a transistor with a strained channel |
| US6503833B1 (en) * | 2000-11-15 | 2003-01-07 | International Business Machines Corporation | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby |
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-
2003
- 2003-01-17 US US10/346,617 patent/US7001837B2/en not_active Expired - Lifetime
-
2004
- 2004-01-13 GB GB0512330A patent/GB2411768B/en not_active Expired - Lifetime
- 2004-01-13 WO PCT/US2004/000981 patent/WO2004068586A1/en not_active Ceased
- 2004-01-13 JP JP2006502832A patent/JP2006517343A/ja active Pending
- 2004-01-13 DE DE112004000146T patent/DE112004000146B4/de not_active Expired - Lifetime
- 2004-01-13 CN CN2004800074546A patent/CN1762056B/zh not_active Expired - Lifetime
- 2004-01-13 KR KR1020057013068A patent/KR101023208B1/ko not_active Expired - Lifetime
-
2006
- 2006-02-17 US US11/356,606 patent/US7701019B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6071784A (en) * | 1997-08-29 | 2000-06-06 | Advanced Micro Devices, Inc. | Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss |
| US6503833B1 (en) * | 2000-11-15 | 2003-01-07 | International Business Machines Corporation | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby |
| US6492216B1 (en) * | 2002-02-07 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Method of forming a transistor with a strained channel |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101023208B1 (ko) | 2011-03-18 |
| GB2411768A (en) | 2005-09-07 |
| US7701019B2 (en) | 2010-04-20 |
| US20040142545A1 (en) | 2004-07-22 |
| DE112004000146T5 (de) | 2006-02-02 |
| KR20050086961A (ko) | 2005-08-30 |
| US20060138479A1 (en) | 2006-06-29 |
| JP2006517343A (ja) | 2006-07-20 |
| US7001837B2 (en) | 2006-02-21 |
| CN1762056A (zh) | 2006-04-19 |
| GB0512330D0 (en) | 2005-07-27 |
| WO2004068586A1 (en) | 2004-08-12 |
| DE112004000146B4 (de) | 2010-05-06 |
| GB2411768B (en) | 2006-04-26 |
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