JP2006516754A - トランジスタ制御表示装置 - Google Patents
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Abstract
【解決手段】装置の第1の金属レベル上に形成されたソースアドレスラインおよびTFTドレイン電極を備えるアクティブマトリックスディスプレイ画素の装置アーキテクチャである。画素電極は第2の隔離された金属レベル上に形成されており、TFTゲート電極およびゲートアドレスラインは第1のレベルおよび第2のレベルの両方から少なくとも1つの誘電体層によって分離されている第3の金属レベル上に形成されている。第2のレベルの上にある画素電極は第1のレベルの上にあるドレイン電極とヴィアホール接続を介して電気的に接続されており、画素コンデンサは第2のレベル上にある画素電極の一部を第3のレベル上にある画素の隣接するラインのゲートアドレスラインの一部と重ね合わせることによって形成されている。装置は好ましくは印刷を用いる方法を使って形成される。
Description
Claims (31)
- 表示媒体、少なくとも部分的に印刷されたトランジスタのアレー、トランジスタのアレーを制御するためのアドレスライン、およびトランジスタのアレーと表示媒体との間に少なくとも部分的に位置している画素電極のアレーであってこれを介して表示媒体のそれぞれの部分がトランジスタによって制御可能となるアレーを備える画素化表示装置であって、それぞれの画素電極はそれぞれのトランジスタを通じて前記アドレスラインのうち1つを介して制御可能であり、また前記アドレスラインの別のものおよび/またはそれに接続されているカウンタ電極と重なり合ってともに静電結合を作り出していることを特徴とする、画素化表示装置。
- アドレスラインが印刷されておりライン幅が60ミクロン未満であり、好ましくは40ミクロン未満であり、さらに好ましくは20ミクロン未満であることを特徴とする、請求項1に記載の装置。
- それぞれのトランジスタはゲート電極を備える薄膜トランジスタであり、それぞれの画素電極は隣接するゲートアドレスラインおよび/またはそれに電気的に接続されているカウンタ電極と重なり合うことを特徴とする、請求項1および2に記載の装置。
- それぞれのトランジスタはソース、ドレインおよびゲート電極を備える薄膜トランジスタであり、それぞれの画素電極は下に設けられているそれぞれのトランジスタのソースまたはドレイン電極のうちの1つと導電性垂直相互接続を介して1つ以上の絶縁層を通じて接続されていることを特徴とする、請求項1に記載の装置。
- 垂直相互接続は直径が60ミクロン未満であり、好ましくは40ミクロン未満であり、さらに好ましくは20ミクロン未満であることを特徴とする、請求項5に記載の装置。
- 隣接する画素電極は40ミクロン未満の距離で、好ましくは20ミクロン未満の距離で、さらに好ましくは10ミクロン未満の距離で隔てられていることを特徴とする、上記請求項のいずれかに記載の装置。
- 画素電極材料が液体から堆積されることを特徴とする、請求項6に記載の装置。
- 隣接する画素電極間の距離は表面エネルギーパターンによって定義されることを特徴とする、請求項7に記載の装置。
- それぞれのトランジスタのドレイン電極は同じゲートアドレスラインおよび/またはそれぞれの画素電極としてのカウンタ電極と重なり合うことを特徴とする、請求項3に記載の表示装置。
- 少なくとも部分的に印刷されたトランジスタのアレー、トランジスタのアレーを制御するためのアドレスライン、および電位がトランジスタに応じるものでありまた少なくとも部分的にトランジスタの上に配置されている画素電極のアレーを備える電子装置であって、それぞれの画素電極はそれぞれのトランジスタを通じて前記アドレスラインのうち1つを介して制御可能であり、また前記アドレスラインの別のものおよび/またはそれが接続されているカウンタ電極と重なり合ってともに静電結合を作り出していることを特徴とする、電子装置。
- 表示媒体は双安定表示媒体であることを特徴とする、請求項1から10のいずれかに記載の装置。
- 装置は電子ペーパーとして使用できることを特徴とする、請求項1から11のいずれかに記載の装置。
- 表示媒体、トランジスタのアレー、トランジスタを制御するためのアドレスライン、およびトランジスタのアレーと表示媒体との間に少なくとも部分的に位置している画素電極のアレーであってこれを介して表示媒体のそれぞれの部分がトランジスタによって制御可能となるアレーを備え、それぞれの画素電極はそれぞれのトランジスタを通じて前記アドレスラインのうち1つを介して制御可能であり、また前記アドレスラインの別のものおよび/またはそれが接続されているカウンタ電極と重なり合ってともに静電結合を作り出している画素化表示装置を製造する方法であって、印刷技術によってトランジスタのアレーの少なくとも1つの素子を形成する工程を含むことを特徴とする方法。
- 印刷技術はインクジェット印刷技術であることを特徴とする、請求項13に記載の方法。
- それぞれの画素電極は印刷技術によって形成されることを特徴とする、請求項13または請求項14に記載の方法。
- トランジスタの少なくとも1つの素子は表面エネルギーパターン形成層上に印刷によって形成されていることを特徴とする、請求項13から15のいずれかに記載の方法。
- 表面エネルギーパターン形成層は直接書込みレーザーパターンニングを含む技術によって形成されることを特徴とする、請求項16に記載の方法。
- トランジスタは半導体層によって第1の方向に接続されているソースおよびドレイン電極を備えており、半導体層は印刷によって定義されて幅が前記第1の方向に120ミクロン未満、好ましくは80ミクロン未満、さらに好ましくは40ミクロン未満とされていることを特徴とする、請求項13に記載の方法。
- それぞれのトランジスタはゲート電極を備える薄膜トランジスタであり、アドレス回路系はゲートアドレスラインを備えており、それぞれの画素電極は隣接するトランジスタのゲートアドレスラインと重なり合っており、重なり合っている領域は表面エネルギーパターン形成層に画素電極およびゲートアドレスラインのいずれか一方または両方を印刷によって形成することで制御されることを特徴とする、請求項13に記載の方法。
- 溶液処理によって形成される下側導電性層と、前記下側導電性層の上に設けられかつそれと導電性相互接続を介して1つ以上の絶縁層を通じて電気的に接続されている上側導電性層とを備える電子装置を製造する方法であって、前記相互接続の作成は、下側導電性層と前記1つ以上の絶縁層とを区別する光溶発技術を使って少なくとも下側導電性層の一部へと下向きに延びる孔を前記少なくとも1つの絶縁層に定義する工程、およびその後前記孔に導電性材料を堆積する工程を含むことを特徴とする方法。
- 前記光溶発技術が、前記1つ以上の絶縁層内に光吸収剤を選択的に充填する工程、および前記光吸収剤が最大の吸収を示す波長の光を使う工程を含むことを特徴とする、請求項20に記載の方法。
- 前記区別する光溶発技術は、下側導電性層と前記1つ以上の絶縁層との間に解放層を設ける工程、および選択的に吸収を行う波長の光を解放層に照射することで解放層が上に設けられている前記1つ以上の絶縁層の一部を基板から離脱させると同時に少なくとも下に設けられている下側導電性層の一部はそのまま残す工程を備えることを特徴とする、請求項20に記載の方法。
- 溶液処理によって形成される下側導電性層と、前記下側導電性層の上に設けられかつそれと導電性相互接続を介して1つ以上の絶縁層を通じて電気的に接続されている上側導電性層とを備える電子装置を製造する方法であって、前記相互接続の作成は、エンボス技術を使って少なくとも下側導電性層の一部へと下向きに延びる孔を前記少なくとも1つの絶縁層に定義する工程、およびその後前記孔に導電性材料を堆積する工程を含むことを特徴とする方法。
- 下側導電性層は薄膜トランジスタ装置のドレインまたはソース電極であり、上側導電性層は前記薄膜トランジスタ装置に結合している画素電極であることを特徴とする、請求項20から23のいずれかに記載の方法。
- 請求項24の方法によって製造される薄膜トランジスタ表示装置。
- 画素電極は下に設けられているゲート電極と重なりあって前記1つ以上の絶縁層の少なくとも1つを介してともに静電結合を作り出していることを特徴とする、請求項25記載の画素化表示装置。
- 少なくとも部分的には印刷技術を用いて基板上に薄膜トランジスタ(TFT)装置のアレーを形成する工程、それぞれのTFT装置のドレインまたはソース電極への上からの接続を残すようにTFT装置のアレー上に1つ以上のパターン形成された絶縁層を設ける工程、およびその後1つ以上のパターン形成された絶縁層上にパターン形成された導電性層を形成することで、それぞれのTFT装置に対しそのドレインまたはソース電極からそのゲート電極の上にまたは隣接するTFTのゲート電極の上に上向きに延びるそれぞれの画素電極を設けることにより開口率を高める工程を含むことを特徴とする、電子装置を製造する方法。
- それぞれのTFT装置はトップゲート構造であり、それぞれの画素電極は隣接するTFT装置のゲート電極との静電容量結合を提供するように配置されていることを特徴とする、請求項27に記載の方法。
- パターン形成された導電性層は前記1つ以上のパターン形成された絶縁層のパターンニング、および1つ以上の下に設けられた層と比較して前記1つ以上のパターン形成絶縁層の前記導電性層の材料に対する相対的親和性を採用することによって作成されることを特徴とする、請求項27または請求項28に記載の方法。
- 請求項27から29のいずれかの方法によって製造されるTFT装置のアレー。
- 請求項30のTFT装置のアレーを備える表示装置。
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