JP2006310858A - 半導体パッケージとともに用いられる改良されたパッケージ基板のための方法およびシステム - Google Patents
半導体パッケージとともに用いられる改良されたパッケージ基板のための方法およびシステム Download PDFInfo
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- JP2006310858A JP2006310858A JP2006121583A JP2006121583A JP2006310858A JP 2006310858 A JP2006310858 A JP 2006310858A JP 2006121583 A JP2006121583 A JP 2006121583A JP 2006121583 A JP2006121583 A JP 2006121583A JP 2006310858 A JP2006310858 A JP 2006310858A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09236—Parallel layout
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09681—Mesh conductors, e.g. as a ground plane
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0969—Apertured conductors
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】半導体パッケージ中で用いられるパッケージ基板用の基板のためのシステムおよび方法が開示される。本発明のシステムおよび方法に従って形成されたパッケージ基板は、改善された信号完全性および品質を示し得る。この信号完全性の増加を達成するために、これらのシステムおよび方法は、高信号密度の領域でパッケージ基板の1つ以上の層から物質を除去することによってパッケージ基板内またはパッケージ基板上の信号線路中のインピーダンスの均一化、すなわち整合を達成することを試み得る。これらの層から物質を除去することは、高信号密度の領域の信号線路のインピーダンスが高信号密度の領域の外側での信号線路のインピーダンスと実質的に整合するように高信号密度の領域内での信号線路のインピーダンスを増加させることに供する。
【選択図】図5
Description
(1)第1層の高信号密度領域に形成された孔の第1組を有する第1層を含んだ層の組を具備する半導体パッケージと共に用いられるパッケージ基板。
前記第1層の高信号密度領域に孔の第1組を形成する、
ことを具備する半導体パッケージと共に用いられるパッケージ基板のための方法。
Claims (22)
- 第1層の高信号密度領域に形成された孔の第1組を有する第1層を含んだ層の組を具備する半導体パッケージと共に用いられるパッケージ基板。
- 前記第1層が第1参照平面層である、請求項1のパッケージ基板。
- 前記第1層がマイクロストリップ構造を具備する、請求項2のパッケージ基板。
- 前記孔の第1組中の各孔が、同じ形状および大きさであって、各孔間のピッチが同じである、請求項3のパッケージ基板。
- 前記層の組が、第2層の前記高信号密度領域に形成された孔の第2組を有する第2層を含む、請求項3のパッケージ基板。
- 前記第2層が第2参照表面層である、請求項5のパッケージ基板。
- 前記第1層および前記第2層がストリップ線構造を具備する、請求項6のパッケージ基板。
- 前記孔の第2組中の各孔が、同じ形状で且つ前記孔の第1組中の各孔と同じ大きさであって、前記孔の第2組中の各孔間のピッチが前記孔の第1組中の各孔間のピッチと同じである、請求項7のパッケージ基板。
- 前記孔の第1組中および前記孔の第2組中の孔が円形または楕円形である、請求項8のパッケージ基板。
- 第1層を含む、層の組を形成し、
前記第1層の高信号密度領域に孔の第1組を形成する、
ことを具備する半導体パッケージと共に用いられるパッケージ基板のための方法。 - 前記第1層から除去されるべき物質の量を決定することをさらに具備し、前記孔の第1組が実質的に前記物質の量を前記第1層から除去することにより形成される、請求項10の方法。
- 前記孔の第1組についての大きさ、形状、ピッチを決定することをさらに具備する請求項11の方法。
- 前記孔の第1組中の各孔が、同じ形状および大きさであって、各孔間のピッチが同じである、請求項12の方法。
- 前記第1層が第1参照平面層である、請求項11の方法。
- 前記第1層がマイクロストリップ構造を具備する、請求項14の方法。
- 第2層の高信号密度領域に孔の第2組を形成することをさらに具備し、前記層の組が前記第2層を含む、請求項14の方法。
- 前記第2層から除去されるべき物質の量を決定することをさらに具備し、前記孔の第2組が実質的に前記物質の量を前記第2層から除去することにより形成される、請求項16の方法。
- 前記孔の第2組についての大きさ、形状、ピッチを決定することをさらに具備する請求項17の方法。
- 前記孔の第2組についての形状、大きさ、およびピッチが、前記孔の第1組についての形状、大きさ、ピッチと同じである、請求項18の方法。
- 前記第2層が第2参照平面層である、請求項17の方法。
- 前記第1層および前記第2層がストリップ線構造を具備する、請求項20の方法。
- 第1参照平面層の高信号密度領域に形成された孔の第1組を有する第1参照平面層を含んだマイクロストリップ構造と、
前記第1参照平面層と、第2参照平面層の高信号密度領域に形成された孔の第2組を有する第2参照平面層と、を含んだストリップ線構造と、
を具備し、
前記孔の第2組中の各孔が、前記孔の第1組中の各孔と同じ形状および大きさであって、前記孔の第2組中の各孔の間のピッチが、前記孔の第1組中の各孔の間のピッチと同じである、
半導体パッケージと共に用いられるパッケージ基板。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/114,362 US7531751B2 (en) | 2005-04-26 | 2005-04-26 | Method and system for an improved package substrate for use with a semiconductor package |
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JP2006310858A true JP2006310858A (ja) | 2006-11-09 |
JP4675818B2 JP4675818B2 (ja) | 2011-04-27 |
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JP2006121583A Expired - Fee Related JP4675818B2 (ja) | 2005-04-26 | 2006-04-26 | パッケージ基板 |
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JP (1) | JP4675818B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010232382A (ja) * | 2009-03-26 | 2010-10-14 | Kyocer Slc Technologies Corp | 配線基板 |
JP2013179692A (ja) * | 2013-05-28 | 2013-09-09 | Kyocer Slc Technologies Corp | 配線基板 |
Families Citing this family (15)
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US7292452B2 (en) * | 2004-06-10 | 2007-11-06 | Intel Corporation | Reference layer openings |
US8212149B2 (en) * | 2008-03-04 | 2012-07-03 | Broadcom Corporation | Mutual capacitance and magnetic field distribution control for transmission lines |
US7921403B2 (en) * | 2008-04-11 | 2011-04-05 | International Business Machines Corporation | Controlling impedance and thickness variations for multilayer electronic structures |
US8549444B2 (en) * | 2008-04-11 | 2013-10-01 | International Business Machines Corporation | Controlling impedance and thickness variations for multilayer electronic structures |
US8863046B2 (en) * | 2008-04-11 | 2014-10-14 | International Business Machines Corporation | Controlling impedance and thickness variations for multilayer electronic structures |
US20100200949A1 (en) | 2009-02-12 | 2010-08-12 | International Business Machines Corporation | Method for tuning the threshold voltage of a metal gate and high-k device |
TWI393495B (zh) * | 2010-12-03 | 2013-04-11 | Adv Flexible Circuits Co Ltd | 訊號傳輸電路板之特性阻抗精度控制結構 |
TWI434634B (zh) * | 2011-08-09 | 2014-04-11 | 中原大學 | Differential mode flat spiral delay line structure |
EP2887776A1 (en) * | 2013-12-18 | 2015-06-24 | Advanced Digital Broadcast S.A. | A PCB with RF signal paths |
US10410984B1 (en) | 2015-06-02 | 2019-09-10 | Sarcina Technology LLC | Package substrate differential impedance optimization for 25 to 60 GBPS and beyond |
US9666544B2 (en) * | 2015-06-02 | 2017-05-30 | Sarcina Technology LLC | Package substrate differential impedance optimization for 25 GBPS and beyond |
US10276519B2 (en) | 2015-06-02 | 2019-04-30 | Sarcina Technology LLC | Package substrate differential impedance optimization for 25 to 60 Gbps and beyond |
CN105025668A (zh) * | 2015-07-02 | 2015-11-04 | 浪潮电子信息产业股份有限公司 | 一种通过添加过孔来实现走线阻抗匹配的方法 |
US9748168B2 (en) * | 2015-10-29 | 2017-08-29 | Nxp Usa, Inc. | Substrate with routing |
CN206807859U (zh) * | 2017-06-13 | 2017-12-26 | 智邦科技股份有限公司 | 用于高速传输的印刷电路板 |
Citations (3)
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JPS63257306A (ja) * | 1987-04-15 | 1988-10-25 | Toshiba Corp | 半導体集積回路パツケ−ジ |
JPH03158002A (ja) * | 1989-11-15 | 1991-07-08 | Nec Corp | 半導体装置 |
JPH0553270U (ja) * | 1991-12-13 | 1993-07-13 | 沖電気工業株式会社 | 多層配線基板 |
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JPH0918097A (ja) | 1995-06-29 | 1997-01-17 | Ibiden Co Ltd | 電子部品搭載用基板 |
US6392160B1 (en) * | 1998-11-25 | 2002-05-21 | Lucent Technologies Inc. | Backplane for radio frequency signals |
US6700076B2 (en) * | 2000-09-28 | 2004-03-02 | Eic Corporation | Multi-layer interconnect module and method of interconnection |
US6937480B2 (en) * | 2001-05-14 | 2005-08-30 | Fuji Xerox Co., Ltd. | Printed wiring board |
US6850133B2 (en) * | 2002-08-14 | 2005-02-01 | Intel Corporation | Electrode configuration in a MEMS switch |
JP4094494B2 (ja) | 2002-08-23 | 2008-06-04 | 新光電気工業株式会社 | 半導体パッケージ |
-
2005
- 2005-04-26 US US11/114,362 patent/US7531751B2/en not_active Expired - Fee Related
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2006
- 2006-04-26 JP JP2006121583A patent/JP4675818B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS63257306A (ja) * | 1987-04-15 | 1988-10-25 | Toshiba Corp | 半導体集積回路パツケ−ジ |
JPH03158002A (ja) * | 1989-11-15 | 1991-07-08 | Nec Corp | 半導体装置 |
JPH0553270U (ja) * | 1991-12-13 | 1993-07-13 | 沖電気工業株式会社 | 多層配線基板 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010232382A (ja) * | 2009-03-26 | 2010-10-14 | Kyocer Slc Technologies Corp | 配線基板 |
JP2013179692A (ja) * | 2013-05-28 | 2013-09-09 | Kyocer Slc Technologies Corp | 配線基板 |
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JP4675818B2 (ja) | 2011-04-27 |
US7531751B2 (en) | 2009-05-12 |
US20060237222A1 (en) | 2006-10-26 |
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