JP2009088063A - 半導体装置およびその設計方法 - Google Patents
半導体装置およびその設計方法 Download PDFInfo
- Publication number
- JP2009088063A JP2009088063A JP2007253155A JP2007253155A JP2009088063A JP 2009088063 A JP2009088063 A JP 2009088063A JP 2007253155 A JP2007253155 A JP 2007253155A JP 2007253155 A JP2007253155 A JP 2007253155A JP 2009088063 A JP2009088063 A JP 2009088063A
- Authority
- JP
- Japan
- Prior art keywords
- region
- wiring
- semiconductor device
- interposer
- characteristic impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】インターポーザ102と、インターポーザ102に搭載された半導体素子108と、を有する半導体装置100であって、平面視で、インターポーザ102は、半導体素子108と重なる第1の領域150と、第1の領域150を除く第2の領域160とからなる。インターポーザ102は、第1の領域150および第2の領域160に跨って形成された少なくともひとつの配線110を有し、配線110の断面形状が、第1の領域150と第2の領域160において異なっている。
【選択図】図1
Description
(第1実施形態)
Z0=√(L0/C0) [Ω]
ここで、「導電体基準面」とは、固定電位を有する導電体を意味する。
導電体基準面および配線間のキャパシタンスCは、真空の誘電率をε0、配線と導電体基準面との間にある絶縁体の比誘電率をεr、導電体基準面と配線間の距離をd、導電体基準面と配線の対向面積をSとすると、よく知られた次、
C=ε0εrS/d [F]
で与えられる。
特性インピーダンスの算出においては、単位長さあたりのキャパシタンスが必要である。配線幅をw[mm]、配線と導電体基準面との距離をh[mm]とすると、配線長さ1cmあたりのキャパシタンスC0は、
C0=10−2×ε0εrw/h [F]
で得られる。
また、配線長さ1cmあたりのインダクタンスは、次式で与えられる。
L0=1.97×10−9×ln(2πh/w) [H]
以上より、配線の特性インピーダンスZ0は、(数2)、(数3)の計算結果を(数4)に代入することにより、求められる。
(第2実施形態)
102 インターポーザ
104 絶縁層
106 ソルダーレジスト
108 半導体素子
110 配線
112 マウント材
114 ワイヤー
116 貫通電極
118 半田ボール
120 樹脂
122 開口
124 プリント基板
150 第1の領域
160 第2の領域
Claims (12)
- インターポーザと、前記インターポーザに搭載された半導体素子と、を有する半導体装置において、
平面視で、前記インターポーザは、前記半導体素子と重なる第1の領域と、前記第1の領域を除く第2の領域とからなり、前記インターポーザは、その内部に前記第1の領域および第2の領域に跨って形成された少なくともひとつの配線を有し、
前記インターポーザの中の前記配線の断面形状が、前記第1の領域と前記第2の領域において異なることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記配線の前記第1の領域における特性インピーダンスは、前記配線の前記第2の領域における特性インピーダンスと実質的に等しいことを特徴とする半導体装置。 - 請求項1または2に記載の半導体装置において、
前記配線の前記第1の領域における幅は、前記配線の前記第2の領域における幅よりも狭いことを特徴とする半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置において、
前記配線の前記第1の領域における厚みは、前記配線の前記第2の領域における厚みよりも薄いことを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記配線の下面は、前記第1の領域と第2の領域で、同一平面上にある半導体装置。 - 請求項1乃至5いずれかに記載の半導体装置において、
前記インターポーザは複数の配線層を含み、
前記配線は、前記第1の領域と前記第2の領域で、異なる配線層に設けられている半導体装置。 - 請求項1乃至6いずれかに記載の半導体装置において、
前記半導体素子は前記インターポーザに、ソルダーレジストおよびマウント材を介して搭載されている半導体装置。 - 請求項1乃至8いずれかに記載の半導体装置において、前記インターポーザが実装されたプリント基板をさらに備える半導体装置。
- 請求項1乃至8いずれか記載の半導体装置において、
前記半導体素子は、ロジック回路の機能を含むLSIである半導体装置。 - 半導体素子を搭載したインターポーザと、前記インターポーザを実装したプリント配線基板からなる半導体装置の設計方法であって、
平面視で、前記インターポーザは、前記半導体素子と重なる第1の領域と、前記第1の領域を除く第2の領域とからなり、前記インターポーザは、その内部に前記第1の領域および第2の領域に跨って形成された少なくともひとつの配線を有し、
前記第2の領域において、前記プリント基板または前記インターポーザの内部の配線層を導電体基準面とした前記配線のキャパシタンスおよびインダクタンスを求めることにより、前記配線の第2の領域における特性インピーダンスを計算し、
前記第1の領域において、前記プリント基板または前記インターポーザの内部の配線層を導電体基準面とした前記配線のキャパシタンスおよびインダクタンス、ならびに前記半導体素子の前記インターポーザと向かい合う面を導電体基準面とした前記配線のキャパシタンスおよびインダクタンスを求めることにより、前記配線の第1の領域における特性インピーダンスを計算し、
前記第2の領域における前記インターポーザの中の前記配線の断面形状と、前記第1の領域における前記インターポーザの中の前記配線の断面形状が異なることにより、前記第1の領域における特性インピーダンスと前記第2の領域における特性インピーダンスを実質的に等しくすることを特徴とする半導体装置の設計方法。 - 請求項10に記載の半導体装置の設計方法であって、
前記プリント基板または前記インターポーザの内部の配線層は、接地層である半導体装置の設計方法。 - 請求項10に記載の半導体装置の設計方法であって、
前記プリント基板または前記インターポーザの内部の配線層は、電源層である半導体装置の設計方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007253155A JP5051836B2 (ja) | 2007-09-28 | 2007-09-28 | 半導体装置およびその設計方法 |
US12/232,889 US8089004B2 (en) | 2007-09-28 | 2008-09-25 | Semiconductor device including wiring excellent in impedance matching, and method for designing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007253155A JP5051836B2 (ja) | 2007-09-28 | 2007-09-28 | 半導体装置およびその設計方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009088063A true JP2009088063A (ja) | 2009-04-23 |
JP5051836B2 JP5051836B2 (ja) | 2012-10-17 |
Family
ID=40506901
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007253155A Expired - Fee Related JP5051836B2 (ja) | 2007-09-28 | 2007-09-28 | 半導体装置およびその設計方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8089004B2 (ja) |
JP (1) | JP5051836B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009246317A (ja) * | 2008-04-01 | 2009-10-22 | Nec Electronics Corp | 半導体装置および配線基板 |
US8453095B2 (en) * | 2011-07-06 | 2013-05-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Systems and methods for creating frequency-dependent netlist |
US8745559B2 (en) | 2011-07-06 | 2014-06-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Systems and methods for creating frequency-dependent netlist |
KR20130064477A (ko) * | 2011-12-08 | 2013-06-18 | 삼성전자주식회사 | 단층 배선 패턴을 포함하는 인쇄회로기판 |
JP2021182567A (ja) * | 2018-08-09 | 2021-11-25 | ソニーセミコンダクタソリューションズ株式会社 | 半導体集積回路および電子機器 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10242716A (ja) * | 1997-02-27 | 1998-09-11 | Kyocera Corp | 高周波用入出力端子ならびにそれを用いた高周波用半導体素子収納用パッケージ |
JP2001127192A (ja) * | 1999-10-27 | 2001-05-11 | Kyocera Corp | 半導体素子搭載用基板 |
JP2001203300A (ja) * | 2000-01-18 | 2001-07-27 | Matsushita Electric Ind Co Ltd | 配線用基板と半導体装置および配線用基板の製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07106759A (ja) | 1993-09-30 | 1995-04-21 | Sony Corp | 薄膜多層基板 |
JP3548022B2 (ja) | 1998-12-03 | 2004-07-28 | 三洋電機株式会社 | 半導体装置 |
US6366467B1 (en) * | 2000-03-31 | 2002-04-02 | Intel Corporation | Dual-socket interposer and method of fabrication therefor |
US7110263B2 (en) * | 2004-03-09 | 2006-09-19 | Intel Corporation | Reference slots for signal traces |
US7750434B2 (en) * | 2005-01-31 | 2010-07-06 | Sanyo Electric Co., Ltd. | Circuit substrate structure and circuit apparatus |
JP2007335607A (ja) * | 2006-06-14 | 2007-12-27 | Sharp Corp | Icチップ実装パッケージ、及びこれを用いた画像表示装置 |
-
2007
- 2007-09-28 JP JP2007253155A patent/JP5051836B2/ja not_active Expired - Fee Related
-
2008
- 2008-09-25 US US12/232,889 patent/US8089004B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10242716A (ja) * | 1997-02-27 | 1998-09-11 | Kyocera Corp | 高周波用入出力端子ならびにそれを用いた高周波用半導体素子収納用パッケージ |
JP2001127192A (ja) * | 1999-10-27 | 2001-05-11 | Kyocera Corp | 半導体素子搭載用基板 |
JP2001203300A (ja) * | 2000-01-18 | 2001-07-27 | Matsushita Electric Ind Co Ltd | 配線用基板と半導体装置および配線用基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5051836B2 (ja) | 2012-10-17 |
US20090084592A1 (en) | 2009-04-02 |
US8089004B2 (en) | 2012-01-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6000317B2 (ja) | 半導体装置 | |
US7531751B2 (en) | Method and system for an improved package substrate for use with a semiconductor package | |
JP4848490B2 (ja) | 伝送線路及びこれを有する配線基板並びに半導体装置 | |
JP5172341B2 (ja) | 基板アッセンブリ、多層回路板アッセンブリ、ボール・グリッド・アレーパッケージ、電子アッセンブリ、基板アッセンブリ内の寄生容量を最小にする方法および基板アッセンブリを製造する方法 | |
US20070158797A1 (en) | Circuit board and electronic assembly | |
JP5891585B2 (ja) | 半導体装置及び配線基板 | |
JP3368870B2 (ja) | パッケージ基板及びこれを備えた半導体装置 | |
JP5051836B2 (ja) | 半導体装置およびその設計方法 | |
US8547681B2 (en) | Decoupling capacitor | |
US20070194434A1 (en) | Differential signal transmission structure, wiring board, and chip package | |
JP4659087B2 (ja) | 差動平衡信号伝送基板 | |
US20090128993A1 (en) | Multi-tier capacitor structure, fabrication method thereof and semiconductor substrate employing the same | |
US20080283286A1 (en) | Printed circuit board | |
JP4927993B2 (ja) | 複合配線基板 | |
JP2001203300A (ja) | 配線用基板と半導体装置および配線用基板の製造方法 | |
US8728874B2 (en) | Method and apparatus for low inductive design pattern | |
CN107360663B (zh) | 可选择对应接地层的电路板结构 | |
WO2015040727A1 (ja) | 半導体集積回路装置 | |
US8049340B2 (en) | Device for avoiding parasitic capacitance in an integrated circuit package | |
JP2005327903A (ja) | 半導体装置 | |
US6969912B2 (en) | Embedded microelectronic capacitor incorporating ground shielding layers and method for fabrication | |
JP5739363B2 (ja) | 配線基板 | |
JP2009246317A (ja) | 半導体装置および配線基板 | |
JP2007129122A (ja) | 半導体装置 | |
KR100601484B1 (ko) | 하이브리드 플립칩 패키지 기판 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20100426 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100517 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101118 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120529 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120629 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120718 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120720 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5051836 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150803 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |